Re: SV Functional Coverage : Instruction sequence?

On Jun 25, 4:18 am, Shenli <zhushe...@xxxxxxxxx> wrote:
Hi all,

When verify a CPU, I encounter a SV functional coverage problem.
I'd like to check whether there are some back-to-back instructions
sequence happened that I am interested in.
Like the instruction sequence:
...
Inst_1 R1, R2
Inst_4 R3, R4
Inst_9 R2, R2
...
But how to define the cover_group? AFAIK, there are control coverage
and data coverage, shall I combine them together to get the
Instruction sequence coverage?

Another questions that always confused me: I have a transaction
generator and monitor(which connected input driver). Shall I get
coverage from transaction generator directly or from the monitor
connected input driver? IMHO, they are the same. But, what's your
opinion?

Any suggestions are welcome!

Best regards,
Davy

As a simple alternative to SV sequences, you may use configurable
verilog component "match_seq" to match clocked sequences of any
events. Note, that the clock, supplied to this component, may be not
an actual design clock but generated "system-level clock" which
syncrhonizes higher-level transactions.


-------------------------------------------------------------
module match_seq (clk, rst_n, seq, match);
parameter BWIDTH = 1; // match sequence length
parameter SCP = 1'b0; // Single Cycle Pattern matching (default :
multicycle)
input clk, rst_n;
input [BWIDTH-1:0] seq;
output match;

reg [BWIDTH-1:0] seq_p, count;

always @(posedge clk) begin
if (!rst_n) count <= BWIDTH;
else begin
seq_p <= seq;
if (seq != seq_p | SCP)
if (seq == 1'b1 << count-1) count <= count-1;
else count <= BWIDTH;
if (count == 0) count <= BWIDTH;
end
end
assign match = (count == 0);

endmodule
-------------------------------------------------------------
For example:
match_seq #3 i_match1 (clk, rst_n, {address==55 & data==66 &
tran==write, address==33 & data==11 & tran==read, address==99 &
data==99 & tran==idle}, match1);

You may add any number of sequence matching components and then cover
only their "match" signals.

Regards,
-Alex

.

Relevant Pages

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    (comp.lang.verilog)
  • Re: Systemverilog covergroup
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  • Re: Systemverilog covergroup
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    (comp.lang.verilog)
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    (comp.lang.verilog)