LogicSim v3.0 Verilog Simulator is Here!
- From: Joe <ngsayjoe@xxxxxxxxx>
- Date: Wed, 13 Jun 2007 07:39:48 -0700
LogicSim v3.0, an affordable and user-friendly Verilog simulator for
ASIC and FPGA design verification is finally here. This is a major
release that contains many new features, updates and bug fixes.
Below is a summary of major features new in this release:
* Added 64-bit simulation time kernel support. In other words,
simulation time unit can now go up to 18,446,744,073,709,551,616,
which previously could only go up to 4,294,967,296.
* Added support for moving signals around with mouse Drag & Drop
in waveform viewer.
* Added support for multi-radix conversion in waveform viewer.
* Added support for sorting signals by signal names in waveform
viewer.
* Added support for pausing simulation for while simulation is
running. This is especially useful for designs that takes hours to
days to simulate.
* Added support for displaying progress of simulation time in
status bar. This is especially useful for designs that takes hours to
days to simulate.
* Added support for displaying partial waveform while simulation
is paused.
As you see, we have improved the project workspace and waveform viewer
substantially in this release. The simulation kernel itself has become
very stable now, which we hardly receive any bug reports. Besides new
features, we have also updated many existing features, and fixed many
important bugs. Please check out the release notes for more info.
I'd like to thank those who continue submitting bugs and feedbacks.
Without them, we would not be able to improve our software.
You can find this press release at: http://www.zeemz.com/blog/
To download LogicSim v3.0, please go to: http://www.zeemz.com/
Joe,
Zeemz, Inc.
.
- Prev by Date: Anonymous Struct Members / Struct Constants
- Next by Date: High level modeling with SystemVerilog
- Previous by thread: Anonymous Struct Members / Struct Constants
- Next by thread: High level modeling with SystemVerilog
- Index(es):
Relevant Pages
|
