Large block visualization

Hi,

Is there a way to vision how a very large block written in Verilog is
connected? It is kind of a schematic tool but Synopsys' GUI tools
don't meet my requirement because it is very hard to trace connection
in that way. For example, it is not possible to trace a state machine
coding in this way.

I may have used a wrong approach in digging into the schematic. Anyone
has experience in understanding a barely documented design?

Thanks

.

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