Re: FlipFlop testbench with reset
- From: mk <kal*@dspia.*comdelete>
- Date: Tue, 06 Mar 2007 16:30:13 GMT
On 6 Mar 2007 08:14:33 -0800, "Verictor" <stehuang@xxxxxxxxx> wrote:
Hi,
When writing a testbench for a simple circuit, e.g., divided-by-2, it
is not desired to have a reset signal on the flip flop (for various
reasons). In this case, the simulation always reports the output as
"x". Is there a way to workaround? Of course, it is easy to include a
reset and simulate the circuit then remove it when the result is good.
But is there a direct way to do that?
Thanks
You can use a force statement at the output of the flop and keep it
for at least one clock cycle so it gets a chance to be clocked in.
Then you can release it. Or you can use an initial statement to set
the initilal value to zero as opposed to X. If you want to keep the
same testbench for the gate level sims too, force is better because
there is no more reg to initialize in gate level netlist.
.
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