Re: Recursive instantiation: a synthesis no no?

Andy Ray wrote:


PS For you viewing pleasure:
the bitionic sort implemented in Verilog 2001 with recursive
instantiation.

I leave the iterative version as an excercise for the reader :-)



I'll take you up on that !

The output is verilog with no recursion (or iteration for that matter).

Cheers,

Andy

I'm trying to understand this example (to see how I could solve
it using MyHDL). After some hacking (on Linux) I was able to run it,
but I got Verilog code with an interface with only outputs, except
clock and reset. Can't be right I guess. The interface starts
as follows:

--
module bitonic (reset, clock, o7, o6, o5, o4, o3, o2, o1, o0);
input reset, clock;
output [3:0] o7;
output [3:0] o6;
output [3:0] o5;
output [3:0] o4;
output [3:0] o3;
output [3:0] o2;
output [3:0] o1;
output [3:0] o0;
wire _126;
wire _120;
...
--

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
module bitonic (reset, clock, o7, o6, o5, o4, o3, o2, o1, o0);
input reset, clock;
output [3:0] o7;
output [3:0] o6;
output [3:0] o5;
output [3:0] o4;
output [3:0] o3;
output [3:0] o2;
output [3:0] o1;
output [3:0] o0;
wire _126;
wire _120;
wire [3:0] _118;
wire [3:0] _117;
wire _116;
wire [3:0] _114;
wire [3:0] _113;
wire _112;
wire _106;
wire _100;
wire [3:0] _98;
wire [3:0] _97;
wire _96;
wire [3:0] _94;
wire [3:0] _93;
wire _92;
wire [3:0] _90;
wire [3:0] _89;
wire _88;
wire [3:0] _86;
wire [3:0] _85;
wire _84;
wire [3:0] _82;
wire [3:0] _81;
wire _80;
wire [3:0] _78;
wire [3:0] _77;
wire _76;
wire [3:0] _73;
wire [3:0] _72;
wire _71;
wire [3:0] _67;
wire [3:0] _66;
wire _65;
wire [3:0] _63;
wire [3:0] _62;
wire _61;
wire [3:0] _59;
wire [3:0] _58;
wire _57;
wire [3:0] _54;
wire [3:0] _53;
wire _52;
wire [3:0] _49;
wire [3:0] _48;
wire _47;
wire [3:0] _44;
wire [3:0] _43;
wire _42;
wire [3:0] _38;
wire [3:0] _37;
wire _36;
wire [3:0] _34;
wire [3:0] _33;
wire _32;
wire [3:0] _30;
wire [3:0] _29;
wire _28;
wire [3:0] _25;
wire [3:0] _24;
wire _23;
wire [3:0] _20;
wire [3:0] _19;
wire _18;
wire _16;
wire _15;
wire [3:0] _13;
wire [3:0] _12;
wire [3:0] _11;
wire [3:0] _10;
wire [3:0] _9;
wire [3:0] _8;
wire [3:0] _7;
wire [3:0] _6;
//(circuit bitonic
assign _126 = (_15 == (_117 < _113));
assign _120 = (_15 == (_118 < _114));
assign _118 = (_116 ? _89 : _81);
assign _117 = (_116 ? _81 : _89);
assign _116 = (_15 == (_89 < _81));
assign _114 = (_112 ? _85 : _77);
assign _113 = (_112 ? _77 : _85);
assign _112 = (_15 == (_85 < _77));
assign _106 = (_15 == (_97 < _93));
assign _100 = (_15 == (_98 < _94));
assign _98 = (_96 ? _90 : _82);
assign _97 = (_96 ? _82 : _90);
assign _96 = (_15 == (_90 < _82));
assign _94 = (_92 ? _86 : _78);
assign _93 = (_92 ? _78 : _86);
assign _92 = (_15 == (_86 < _78));
assign _90 = (_88 ? _72 : _43);
assign _89 = (_88 ? _43 : _72);
assign _88 = (_15 == (_72 < _43));
assign _86 = (_84 ? _73 : _44);
assign _85 = (_84 ? _44 : _73);
assign _84 = (_15 == (_73 < _44));
assign _82 = (_80 ? _66 : _37);
assign _81 = (_80 ? _37 : _66);
assign _80 = (_15 == (_66 < _37));
assign _78 = (_76 ? _67 : _38);
assign _77 = (_76 ? _38 : _67);
assign _76 = (_15 == (_67 < _38));
assign _73 = (_71 ? _62 : _58);
assign _72 = (_71 ? _58 : _62);
assign _71 = (_16 == (_62 < _58));
assign _67 = (_65 ? _63 : _59);
assign _66 = (_65 ? _59 : _63);
assign _65 = (_16 == (_63 < _59));
assign _63 = (_61 ? _53 : _48);
assign _62 = (_61 ? _48 : _53);
assign _61 = (_16 == (_53 < _48));
assign _59 = (_57 ? _54 : _49);
assign _58 = (_57 ? _49 : _54);
assign _57 = (_16 == (_54 < _49));
assign _54 = (_52 ? _13 : _12);
assign _53 = (_52 ? _12 : _13);
assign _52 = (_16 == (_13 < _12));
assign _49 = (_47 ? _11 : _10);
assign _48 = (_47 ? _10 : _11);
assign _47 = (_15 == (_11 < _10));
assign _44 = (_42 ? _33 : _29);
assign _43 = (_42 ? _29 : _33);
assign _42 = (_15 == (_33 < _29));
assign _38 = (_36 ? _34 : _30);
assign _37 = (_36 ? _30 : _34);
assign _36 = (_15 == (_34 < _30));
assign _34 = (_32 ? _24 : _19);
assign _33 = (_32 ? _19 : _24);
assign _32 = (_15 == (_24 < _19));
assign _30 = (_28 ? _25 : _20);
assign _29 = (_28 ? _20 : _25);
assign _28 = (_15 == (_25 < _20));
assign _25 = (_23 ? _9 : _8);
assign _24 = (_23 ? _8 : _9);
assign _23 = (_16 == (_9 < _8));
assign _20 = (_18 ? _7 : _6);
assign _19 = (_18 ? _6 : _7);
assign _18 = (_15 == (_7 < _6));
assign _16 = 1'b0;
assign _15 = 1'b1;
assign _13 = 4'b1010;
assign _12 = 4'b0000;
assign _11 = 4'b1011;
assign _10 = 4'b1111;
assign _9 = 4'b0010;
assign _8 = 4'b0101;
assign _7 = 4'b0011;
assign _6 = 4'b0001;
assign o7 = (_126 ? _113 : _117);
assign o6 = (_126 ? _117 : _113);
assign o5 = (_120 ? _114 : _118);
assign o4 = (_120 ? _118 : _114);
assign o3 = (_106 ? _93 : _97);
assign o2 = (_106 ? _97 : _93);
assign o1 = (_100 ? _94 : _98);
assign o0 = (_100 ? _98 : _94);
//endcircuit bitonic)
endmodule

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