comp.lang.verilog

Date Index

Using Hyper Terminal to send& capture data, Smith
- Re: Using Hyper Terminal to send& capture data, Mark Norton
Generating UCF file for the UART module, Smith
gtkwave 3.0.5 for win32, mk
Mixed language simulation in VCS, K.Hemanth
ncverilog and other LDV tools, K.Hemanth
Verification of models, Ani
Named event module ports?, Robert Au
- Re: Named event module ports?, sharp
  - Re: Named event module ports?, Robert Au
    - Re: Named event module ports?, sharp
easy way for executing commands sequenced?, poldi
- Re: easy way for executing commands sequenced?, gabor
  - Re: easy way for executing commands sequenced?, poldi
How/when are defparams applied?, Mike Pearson
- Re: How/when are defparams applied?, Michael
How to describe a register file mux compactly., Paul Marciano
- Re: How to describe a register file mux compactly., John_H
  - Re: How to describe a register file mux compactly., Paul Marciano
    - Re: How to describe a register file mux compactly., sharp
    - Re: How to describe a register file mux compactly., Paul Marciano
A very cool ftp, water9580@xxxxxxxxx
sine wave generation using verilog, kunal
- Re: sine wave generation using verilog, nemgreen
- Re: sine wave generation using verilog, Andy Peters
Filtered Back Projection Algorithm (FBP Algorithm), Bapaiah Katepalli
- Re: Filtered Back Projection Algorithm (FBP Algorithm), Marc Reinig
deriving microarchitecture from Specs, anand
- Re: deriving microarchitecture from Specs, Jeremy Ralph
- Re: deriving microarchitecture from Specs, mk
modeling delays in RTL, anand
- Re: modeling delays in RTL, gabor
  - Re: modeling delays in RTL, gtwrek@xxxxxxxxx
- Re: modeling delays in RTL, Mike Treseler
  - Re: modeling delays in RTL, anand
  - Re: modeling delays in RTL, anand
  - Re: modeling delays in RTL, johnp
SystemVerilog problem?, Davy
- <Possible follow-ups>
- SystemVerilog problem?, Davy
  - Re: SystemVerilog problem?, Ajeetha
  - Re: SystemVerilog problem?, Jonathan Bromley
  - Re: SystemVerilog problem?, ABC
Is this code works like this..., dipesh.trivedi
- Re: Is this code works like this..., subin
- Re: Is this code works like this..., Jonathan Bromley
  - Re: Is this code works like this..., dipesh.trivedi
Re: testbenches in Verilog for I2C ctrl, Jerry
Implementing TCP 2MSL timer in Verilog, kb33
- Re: Implementing TCP 2MSL timer in Verilog, Steve Pope
browsing the model hierarchy with pli routines, mk
- Re: browsing the model hierarchy with pli routines, ramesh
Re: Reset or not to reset, Steve Pope
- Re: Reset or not to reset, Chris F Clark
  - Re: Reset or not to reset, Steve Pope
    - Re: Reset or not to reset, Mike Treseler
    - Re: Reset or not to reset, Steve Pope
I2C Question, junk_no_spam
- Re: I2C Question, gabor
decode this code., dipesh.trivedi
- Re: decode this code., Mike Lewis
  - Re: decode this code., dipesh.trivedi
question regarding SV always_ff and 'blocking timing control', Suman
- Re: question regarding SV always_ff and 'blocking timing control', Jonathan Bromley
  - Re: question regarding SV always_ff and 'blocking timing control', dipesh.trivedi
home to pass unix variable into ncverilog testbench, junk_no_spam
- Re: home to pass unix variable into ncverilog testbench, Jeremy Ralph
- Re: home to pass unix variable into ncverilog testbench, sharp
Unsupported verilog construct with synopsys DC?, Fazela
- Re: Unsupported verilog construct with synopsys DC?, John_H
  - Re: Unsupported verilog construct with synopsys DC?, Fazela
    - Re: Unsupported verilog construct with synopsys DC?, Jonathan Bromley
    - Re: Unsupported verilog construct with synopsys DC?, Jonathan Bromley
    - Re: Unsupported verilog construct with synopsys DC?, Fazela
Re: USB interface between computer and FPGA, Smith
testbench of serial interface(UART), Smith
- Re: testbench of serial interface(UART), Mike Treseler
  - Re: testbench of serial interface(UART), mk
  - Re: testbench of serial interface(UART), Smith
verilog task call in vhdl, vinay . k22914125
- Re: verilog task call in vhdl, sharp
SPYGLASS Tutorial???, mkjindal@xxxxxxxxx
A diff on IEEE 1364-2001 & IEEE 1364-2005 standards, Jogi
blocking -nonblocking with RHS delay que., K.Hemanth
- Re: blocking -nonblocking with RHS delay que., Jonathan Bromley
Estimate gate count in Verilog?, Davy
- Re: Estimate gate count in Verilog?, General Schvantzkoph
  - Re: Estimate gate count in Verilog?, MikeStanley
FSM design using Verilog, harshaperla
interacting state machines, ravi
Behavioral model of SPI EEPROM, muthusnv
- Re: Behavioral model of SPI EEPROM, Michael
  - Re: Behavioral model of SPI EEPROM, comp.lang.verilog
Verilog2001 $signed question, Davy
- Re: Verilog2001 $signed question, mk
- Re: Verilog2001 $signed question, sharp
  - Re: Verilog2001 $signed question, Davy
The 3rd International Electronics Design Contest for Students, jamil . khatib
sharing constants across modules/testbenches, Jason Zheng
- Re: sharing constants across modules/testbenches, Ajeetha
  - Re: sharing constants across modules/testbenches, Jason Zheng
    - Re: sharing constants across modules/testbenches, Jonathan Bromley
System Verilog Questions, katelman
- Re: System Verilog Questions, Ajeetha
  - Re: System Verilog Questions, Enchanter
  - Re: System Verilog Questions, katelman@xxxxxxxxx
    - Re: System Verilog Questions, Ajeetha
USB control packet, Pinhas
STA, venkatesh . kudumula
- Re: STA, Enchanter
Parametrized memory module, Pulzar
- Re: Parametrized memory module, John_H
  - Re: Parametrized memory module, Pulzar
    - Re: Parametrized memory module, sharp
Searching pre-compiled version of GPL CVer simulator for windows, Tom Parson
Re: Inferring Xilinx synthesis results - Help required!, paul . sw . lee
Re: returning multiple values from VPI task?, D Roberts
Re: negative hold time, skyworld
- Re: negative hold time, Jerome
Re: How does always block add a latch, Jeremy Ralph