How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
- From: "Mr. Ken" <Mr. Ken@asdf>
- Date: Wed, 31 May 2006 09:05:07 +0800
My task is to scale up a 9-bit data by 17/sqrt(21) (= 3.7097), with the
best precision possible. Without considering clipping and range issues, I
am using multiplication by 59/16, which gives 0.599% error. What better
approach can I use?
I am going to implement the calculation in ASIC, thus less complexity is
what I am expecting.
.
- Prev by Date: Re: New to Verilog, Help with Serial Com and Control Lines
- Next by Date: How does always block add a latch
- Previous by thread: SystemVerilog Coverage iff
- Next by thread: How does always block add a latch
- Index(es):
Relevant Pages
|
