Re: verilog multidimentional arrays

Verilog-2001 supports multi-dimensional arrays and arrays of nets, but
you still cannot connect an entire array to a port. You can only
connect scalars or vectors to ports. The arrays of nets were primarily
intended for connection to multiple module instances created by
generate loops.

SystemVerilog allows connection of entire arrays to ports (which is
related to the fact that it also allows you to assign entire arrays to
each other).

.

Relevant Pages

  • Fully definable ports of array of std_logic_vectors?
    ... ports which are arrays of std_logic_vectors, ... different array and vector lengths. ...
    (comp.lang.vhdl)
  • Re: Array Ports
    ... IEEE1364-2001 declares it illegal to use arrays as ports. ... ModelSim obviously won't. ...
    (comp.lang.verilog)
  • Re: verilog multidimentional arrays
    ... There are some tricks one can use to map an array to a port. ... Verilog-2001 you can use arrays within the module then for the ports ... for example time sliced state-machines, ...
    (comp.lang.verilog)
  • Re: 64-bit wide multiple port instances
    ... closest you *might* get is the use of predefined interfaces in SystemVerilog ... to have 2-D ports but they just aren't supported in the language. ... multi-dimensional arrays as ports work just fine in ... You can also use "real" types (and arrays of reals) on ports too. ...
    (comp.lang.verilog)
  • Re: how to implement variable ports with variable width?
    ... > width of the port is also variable (but same for all ports). ... - use a configuration package where you define an array of arrays ... two-dimensional arrays and just assign accordingly. ... I would strongly suggest the second solution, ...
    (comp.lang.vhdl)