local module scopes and name spaces


I'm playing around with writing a verilog compiler(translator) and I
have a few questions about local module scopes and name spaces.

For the following trivial module_declarations:

module m0(out0, in0, in1);
output out0;
input in0, in1;
wire out0, in0, in1;

module m1(.po0(out0), .pi0(in0), .pi1(in1));
output out0;
input in0, in1;
wire out0, in0, in1;

1) Am I correct in thinking that when I encounter a module_declaration,
that I have a new scope and that this scope has 2 name spaces - the
module name space and the port name space?

2) For module m0 above, all of out0, in0, and in1 are entered into the
module's port name space because of the port (input/output)
declarations and also all of out0, in0, and in1 are entered into the
module's module name space because of the net declarations?

3) For module m1 above, the same goes as in 2)? What about the
externally-visible port names po0, pi0, and pi1? They are just part of
the module's module name space?

I am trying to put this together from the 1364-1995 spec:

<excerpt from 1364-1995, 3.11 Name spaces>
The module name space is introduced by the module, macromodule, and
primitive constructs. It unifies the definition of functions, tasks,
named blocks, instance names, net type of declaration, and register
type of declaration....

The port name space is introduced by the module, macromodule,
primitive, function, and task constructs. It provides a means of
structurally defining connections between two objects that are in two
different name spaces. The connection can be unidirectional (either
input or output) or bidirectional (inout). The port name space
overlaps the module and the block name spaces. Essentially, the port
name space specifies the type of connection between names in different
name spaces. The port type of declarations include input, output, and
inout (see 12.3). A port name introduced in the port name space may be
reintroduced in the module name space by declaring a register or a wire
with the same name as the port name.

<excerpt from 1364-1995, 12.5 Scope rules>
The following four elements deÞne a new scope in Verilog:
-Named blocks
An identifier shall be used to declare only one item within a scope.
This rule means it is illegal to declare two or more variables that
have the same name, or to name a task the same as a variable within the
same module, or to give a gate instance the same name as the name of
the net connected to its output.

Thanks in advance,


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