Re: Why aren't the forth people doing this?

From: Bernd Paysan <bernd.paysan@xxxxxx>
Date: Thu, 28 Jun 2007 10:10:45 +0200

Frank Buss wrote:

Bernd Paysan wrote:

The design Chuck showed at EuroForth 6 years ago at least had normal CMOS
gates inside.

I think the Muller C gate can be implemented with normal CMOS, too.

No, with "normal CMOS gates" I mean that a NAND consists of four
transistors, two parallel PMOS, and two serial NMOS.

--
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/
.

References:
- Why aren't the forth people doing this?
  - From: pettitj
- Re: Why aren't the forth people doing this?
  - From: Elizabeth D Rather
- Re: Why aren't the forth people doing this?
  - From: Frank Buss
- Re: Why aren't the forth people doing this?
  - From: Bernd Paysan
- Re: Why aren't the forth people doing this?
  - From: Frank Buss

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Re: Why arent the forth people doing this?
... I think the Muller C gate can be implemented with normal CMOS, ... idea is that the output changes to 1, if all inputs are 1 and it changes to ... dual-rail signalling uses C gates, so it is possible with standard CMOS, ...
(comp.lang.forth)
Re: CPU design
... needs less gates than in pure VHDL. ... fast, so I can design a very orthogonal CPU, which maybe needs even less ... Any ideas to reduce the instruction set even more, ... Frank Buss, fb@xxxxxxxxxxxxx ...
(comp.arch.fpga)