Re: Why aren't the forth people doing this?

Bernd Paysan wrote:

The design Chuck showed at EuroForth 6 years ago at least had normal CMOS
gates inside.

I think the Muller C gate can be implemented with normal CMOS, too. The
idea is that the output changes to 1, if all inputs are 1 and it changes to
0, if all inputs are 0. For a 2 input Muller C gate, with the inputs A and
B, and the output C, the logic function is C=A*B+A*C+B*C (where *=AND and
+=OR).

dual-rail signalling uses C gates, so it is possible with standard CMOS,
too: http://www.eetimes.com/editorial/2000/coverstory0005.html

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Frank Buss, fb@xxxxxxxxxxxxx
http://www.frank-buss.de, http://www.it4-systems.de
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