Re: Why aren't the forth people doing this?

Elizabeth D Rather wrote:

pettitj@xxxxxxxxx wrote:
http://www.physorg.com/news102087207.html


They are: http://www.intellasys.net/index.php

It is parallel, but has a very different concept. Every core of the
IntellaSys SEAforth chip has its own RAM and ROM, but the CPU from Vishkin
uses the PRAM concept. See
http://www.umiacs.umd.edu/users/vishkin/XMT/spaa07paper.pdf for a more
detailed description and the Wikipedia article about PRAM:
http://de.wikipedia.org/wiki/PRAM (I'm sorry, the German article is more
detailed than the English article).

A very interesting concept of the SEAforth chip is that it is fully
asynchonous. I assume they are using something like dual-rail signalling or
the Muller C gate for implementing this design.

--
Frank Buss, fb@xxxxxxxxxxxxx
http://www.frank-buss.de, http://www.it4-systems.de
.