Re: Structured Programming using Forth

J Thomas wrote:
No. But first I should point out that I'm not really up on the
competition here. I'm vaguely interested in Forth chips because I'm
interested in Forth. Jeff Fox can make wonderful claims for Forth
chips and I wouldn't know whether he's claiming things that are
routine for competing nonForth chips.

It was never clear to me what processors his chips were supposed to compete with. Discussions about his chips tended to focus on a single attribute at a time. So if we were discussing speed, he would give some benchmark (such as memory cycle time) and compare it to an X. Then if the discussion shifted to addressable RAM, he would compare it to a Y. Someone else brings up power dissipation, and he would compare it to a Z. The problem is that when you step backward and try to find the mythic XYZ processor it competes against, it doesn't exist.

So what was the competition? It was never clear.

I'm going to suppose that Chuck has kept improving chips so that the
new chip will also be far beyond anything in it price range. A chip
with 25 processors will cost less than 25 times as much as a chip with
1 processor because things like pins and packaging are part of the
cost, and also things are smaller now, so I will optimisticly suppose
that produced in large numbers they could bring it down to a couple
dollars a shot.

Of course I'm being optimistic.

That's an understatement. The price is more like $20 for 1000. At least that's what this article from last year says:

http://tinyurl.com/2jdyrm

I guess if you look at it from a cost-per-processor perspective, it means that each processor is 83 cents. But it's important to understand the class of each individual processor in the SEAforth 24 chips. Each processor has a 9-bit PC, which limits one to 512 words of program memory. They gain some efficiency by packing multiple instructions per word, but there are rules for that so you can't just multiply the number of program words by some constant.

The small program size *demands* that any non-trivial application be spread across multiple processors. And then you hit the next big limitation-- each processor can only communicate with its nearest neighbor. Further, processors on the edge are likely going to be used for I/O and interior processors for computation. So part of designing an application is going to be to "floor plan" where each process will be physically placed on the chip.

And on top of all this, it appears to me (and I welcome correction from anyone who knows better) that although the tools used to program the SEAforth chips are in Forth, that you really aren't programming in what most would think as Forth. It's more like an assembly language that just happens to have a Forth flavor. You see this in their preliminary applications guide, where the user is told about tricks like saving program memory by replacing a literal zero with a "dup dup xor" sequence, carefully placing "." (NOP) to generate the most efficient code, and synthesizing "-" from "+" and "not".

I don't have any problem with any of this and any assembly language programmer is going to be able to adapt quickly. But how will the average Forth programmer handle it? How will non-Forth programmers adapt to it?

This is why I say the success of the SEAforth chips is entirely dependent on the quality of tools, models, training, and other support Intellasys provides. The skill set one needs to effectively use one of these $20 chips is different from what I believe most engineers and programmers are currently used to. And if it's *too* different and the tools, models, training, and support is poor, then they aren't going to sell chips.

You seem to have this abstract view of the SEAforth chips. But architecture matters. The architecture that makes SEAforth unique and powerful is also what makes designing applications for it to be fundamentally different. So anything Intellasys can do to make it easier is going to pay off big for them. Conversely, if they are inadequate in this area... well, let's just hope the Indigita and OnSpec product lines can sustain them.

When I as an engineer am asked to choose a processor for a product, I am
expected to choose a processor appropriate for the task. If the task
only takes 4% of the processor, then it is not appropriate.

No, it's appropriate if it will do the job you need done and it's the
cheapest alternative factoring in all your expenses.

But it isn't the cheapest alternative. For $20, I have a number of options that *easily* favorably compete in the same space the Intellasys chips do. If my application is primarily driven by software, I can put together a 200MHz ARM9 system for that price. If I need more speed for signal processing applications, I can go to a DSP-based system for that price. If I decide I want more specialized hardware, I can go to a FPGA and instantiate what I need (and instantiate as many processors as I need) for that price.

So here's the choice: I can choose a conventional processor, conventional DSP, conventional FPGA, or some blend of these. I can use tools and models I'm familiar with and that have been proven to work in countless designs. I can enjoy the competition of third-party support of tools, both proprietary and open source. And most important, I can make predictions such as how long development will take.

Or I can use the SEAforth chip. I can have a proprietary single-sourced and exotic design that is unfamiliar. I will be *forced* (it isn't an option) to rethink my applications as a system of many small cooperative processes, floor-plan those processes, and then write code that isn't much higher in level than assembly language. I don't know what debugging tools exist other than the simulator. And I don't know how to even estimate how long it will take me to get up to speed on this platform and then how long it will take to build my application.

I'm not dissing the chip. I think the architecture is cool and I can imagine all sorts of applications for this. But I'm also realistic.

Back when computing power was expensive, when an hour of computing
time cost ten times as much as n hour of a programmer's time, you
could spend 5 hours reducing a run-once program's time from 2 hours to
1 hour and your cost was justified. Those days are gone. Now you can
afford to wast 96% of your processor time provided the job gets done.

You're thinking of desktop systems, not embedded systems. Desktop systems enjoy this kind of over-design because they are general purpose; you might be word processing with 4% CPU utilization one minute and the next minute your mixing down your album and running at 100% CPU utilization.

Most embedded systems aren't like that. Most embedded systems are purpose-built. They are designed to do one thing, and often cost does matter. So that 4% CPU utilization you're talking about isn't something that later one you might grow into. It's 4% now and will be 4% forever-- or at least until the product's lifetime ends. So you've over-designed a system, with a CPU that is 96% wasteful.

Similarly, if your boss is deciding whether to use you on a project,
he doesn't think "Is this going to use all of John's abilities? I'd
hate to have John doing work that doesn't challenge him completely.".
But he might think "Is this project so easy that I can trust it to the
guy who gets half John's rate?". He doesn't care that you know a
hundred languages and will use at most 5 on his project. He cares that
you can do a superb job in half the hours.

No, actually that's not true. My boss *does* care if I'm going to effectively use my abilities. That's because as a company we have limited bandwidth and thus can only take on a certain number of projects. If I'm doing work on a project that a more junior engineer can also do, it represents time that I'm not available to take on larger projects that have the potential of bringing in more money. The more junior engineer might not finish as quickly, but if that project is being billed at $x and the project I would work on is being billed at $x+n, then you tell me what makes more sense.

If doing more with less is vital, you could go to Intellasys and ask
for a custom chip with just 1 processor, or just 5 processors, the
minimum you need. Maybe that will fit your needs better than the 25-
processor chip. I'd expect you'd do better to find a cheaper
alternative from some competitor. What you want is something cheaper
that will do the job -- you don't care about using the weakest
processor that you can get by with unless it's cheaper, right?

I care about picking the processor that matches requirements. If the processor doesn't match requirements, then that is a red flag and needs to be reviewed. "Cheaper" is only one metric I care about. Depending on the project, I might care about how much power it takes up or how much power it dissipates as heat. I might care about how many I/O pins it offers. I might care about how much program and RAM space (and how those spaces are organized). I might care about how much external circuitry is needed to make the processor actually work. I might care about what support tools (compilers, hardware and software debuggers, operating systems, libraries) are available for it. If the part is unfamiliar to me, I might care if there is a field engineer I can call on to answer questions. I might even care about the physical size of the chip or what mounting technology is used.

It *all* matters.

Intellasys needs to pay attention to the needs of people like you. All
people like me are good for to them is to perhaps get the attention of
people like you -- the more open-minded ones, who won't be put off by
the source.

What is going to put people off of the SEAforth chips are undelivered promises or an architecture that is too difficult/weird/strange to write real-world applications for. Tools, models, training, and support will matter.

As for me, I'm open-minded an enthusiastic. I can't wait to evaluate these chips and see where they excel-- and where they fail. I'm all about finding the edges.
.

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