LSE64 - An example

John Passaniti wrote:

Actually, very little needs to be done other than for you to publish the design notes you presumably have, a glossary of the words in your system, and maybe some sample code.

Most of my LSE64 code operates hardware through comedilib bindings, so it might not be especially edifying if you don't know the hardware or comedilib. But this little thing pokes at *simulated* hardware by producing SPICE statements in ASCII, so maybe it's a little easier to understand. It's separated into two source files: a configuration file for the specific test, and a generic clock generation module. First the configuration:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# $Id: PumpDACtest.lse,v 1.4 2006/04/12 18:04:37 jpd Exp $

# Generate clocks for DAC test

" ClockGen.lse" load

# Parameters for serial data interface

1e7 frequency !
1e-8 risefall !
0.0 3.3 levels

# Standard stuff

" clk" clock
" reset" reset

# Test value for register

" Din" sequence{
16 5 bits
}sequence

# Load the register, wait, enable the DAC

" load" pulse
cycle
3.3 0 levels
" QRST" pulse
cycle
0 3.3 levels
" Enb" pulse

bye

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Ok, and now for the part that does the work:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

# $Id: ClockGen.lse,v 1.1 2006/02/04 05:21:12 jpd Exp $

variables: frequency risefall 0level 1level step
1 step !

# set voltage levels for zero and one
# zero one high levels yields nothing
levels : 1level ! 0level !

# output name and connections for a voltage source
# name =source yields nothing
=source : char V put dup ,t sp ,t sp 0 , sp

# Output logic 1 or zero voltage
# =1 yields nothing
# =0 ditto
=1 : 1level @ ,. sp
=0 : 0level @ ,. sp

# generate start of pulse command
# =pulse( yields nothing
=pulse( : " pulse(" ,t =0 =1

# output time of 1/2 cycle minus transition time
# =pw/2 yields nothing
=pw/2 : 0.5 frequency @ /. risefall @ -. ,. sp

# output rise/fall time
# =rf yields nothing
=rf : risefall @ ,. sp

# output pulse period
# =per yields nothing
=per : 1.0 frequency @ /. ,. sp

# output a closing )
# =) yields nothing
=) : char ) put

# Make master clock
# name clock yields nothing
clock : =source =pulse( =pw/2 =rf =rf =pw/2 =per =) nl

# Generate initial reset
# name reset yields nothing
reset : =source =pulse( =per =rf =) nl

# compute time of current step
# (now) yields time
(now) : step @ float frequency @ /.

# Generate current time
# =now yields nothing
=now : (now) ,. sp

# Generate current time plus rise/fall time
# =now+ yields nothing
=now+ : (now) risefall @ +. ,. sp

# Move time forward one step
# cycle yields nothing
cycle : step @ 1 + step !

# =pwl( yields nothing
=pwl( : " pwl(" ,t

# Start a PWL for a bit sequence
# name sequence{ yields nothing
sequence{ : =source =pwl( 0 , sp =0 =now =0

=bit : =now+ =1 cycle =now =1
=bit : then =now+ =0 cycle =now =0
=lsb : nl char + put sp dup 2 / swap 1 & 0= =bit
bits : =lsb iterate 0= || error( " Not enough bits for value" ,t nl )error

}sequence : =) nl

# Generate a pulse at the current cycle
# name pulse yields nothing
pulse : sequence{ =now+ =1 cycle =now =1 =now+ =0 =) nl

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

And the result is:

[Tanuki:DeltaSigmaChip/Schematic/Simulation] jpd% lse64 PumpDACtest.lse
Vclk clk 0 pulse(0 3.3 4e-08 1e-08 1e-08 4e-08 1e-07 )
Vreset reset 0 pulse(0 3.3 1e-07 1e-08 )
VDin Din 0 pwl(0 0 1e-07 0
+ 1.1e-07 0 2e-07 0
+ 2.1e-07 0 3e-07 0
+ 3.1e-07 0 4e-07 0
+ 4.1e-07 0 5e-07 0
+ 5.1e-07 3.3 6e-07 3.3 )
Vload load 0 pwl(0 0 6e-07 0 6.1e-07 3.3 7e-07 3.3 7.1e-07 0 )
VQRST QRST 0 pwl(0 3.3 8e-07 3.3 8.1e-07 0 9e-07 0 9.1e-07 3.3 )
VEnb Enb 0 pwl(0 0 1e-06 0 1.01e-06 3.3 1.1e-06 3.3 1.11e-06 0 )

And this is the kind of thing that LSE64 gets done. Nothing really cool or exciting. The cool and exciting part starts when the techs bolt the product to the top of the rocket...

--
John Doty, Noqsi Aerospace, Ltd.
--
In theory there is no difference between theory and practice. In practice there is. -Yogi Berra
.

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