SEAforth system scaling questions

As I was designing ethernet/IP layer 2/3 switching for the kind of
processing I've divined from the current level of available information
on the SEAforth processors, I generated a list of questions which will
have a big impact on how that design progresses. So this isn't a
request for guesses, but rather a way to draw out some parameters which
aren't currently clear, but could drive the design in very different
directions.

1. Inter-chip API and performance
We have some indications of what it's like to move code/data between
nodes within a chip; what happens if the system design requires more
than one chip? Is the API similar, or very different? How much slower
is it to cross a chip boundary?

2. Return and operand stack depths
My MuP21 has very, very thin stacks. The F21 has relatively deep
stacks. In some post-F21 comments, Mr. Moore commented that the sweet
spot was in between. How deep did the SEAforth stacks end up being?

3. External memory & and its controller
It sounds like one of the CPUs will act as a memory controller to an
external part. For L2/3 switching, some of the tables are simply too
large to fit in local CPU RAM, so how expensive is it to reach this
external RAM from various nodes on the chip, and what sort of memory
access performance is expected to the external device? How big can it
be?

4. Internal memory performance
Does the internal RAM support full speed operation? If I do a @ as the
last op in a word, and reference the result in the first op of the next
word, what sort of blocking and delay would I expect? Is interlocking
always done for me, or are there cases where I must pad with nops?

5. Cooperation with more than one neighbor
There are some natural decompositions of functionality which result in
a node not knowing from which direction a request will come next. I
can imagine polling types of behavior which handle this, but at a cost
in latency and power consumption. Is there a mechanism for a CPU to
block in such a way that it can awake based on more than one possible
direction?

6. External device speed
There appear to be SPI and parallel ports to interface to the outside
world. What speeds can these achieve? Which of these become
unavailable if you need to interconnect more than one chip?

7. Spread of I/O access
Related question--which CPUs in the chip get access to which parts of
this I/O?

Like I said, I don't expect anyone except an Intellasys person to be
able to answer these questions. But it can still be useful to tabulate
the system parameters which are currently unknown.

Regards,
Andy Valencia

.

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