Re: XA1541 trouble



Hi Christian,

beside the comments given to Joe's post I
would like to give some detailed side info
to your nice analysis report.

Christian R. Larsen schrieb:
The situation: I'm on the newer Dell PC (newer dual core machine).

Ok.

I ran through the various tests specified in the XCtest manual chapter
3. These were all run in ECP-mode and EPP-mode with the same result.

Test 1:
The adaptor is removed, nothing connected to the parallel port.
When altering the four outputs, the inputs still remain the same.

Ok, this is because no drive is connected
and switched to on. Are the lines detected
as constant high or as constant low?

I tried letting it detect port modes - for some reason, it detects a
X1541 cable and sets this option. Then, when running the same tests as
before, all input lines change as they should.

Cable autodetection does only work reliably,
when a) a cable or adaptor is plugged into
the LPT port b) the cable is not defective
and c) when a drive is connected and
switched to on.
The behavior of the test is correct, when a
X1541 is configured as the documentation
tells.

Test 2:
Only the adaptor in place - no cable connected.
All four outputs set to low one at a time - all other outputs are kept
at high. Atn, Data and Reset inputs all change mode following their
corresponding outputs. Clock doesn't - Clock's always high.

Hmmmm, you did configure the cable type to
XA1541 before, right?

Currently I see two possibilities. Either
the input line is not working or not
connected correctly. Or the output part of
the XA1541 cable has got a malfunction.

Test 3:
The adaptor in place, the cable connected, the drive switched on.

Drive-Loop test:
All four outputs set to low one at a time - all other outputs are kept
at high.
Failed. Atn and Data change mode following their corresponding
outputs. Clock input doesn't change

Ok, this reflects the result from Test 2,
either the input line doesn't work, or it is
the output line not beign able to create a
low level at all.

and when altering the Reset
output, both Clock, Data and Reset inputs shifts state.

This reporting belongs to the next test!

Drive-Reset test:
Passed.

This is, what you said above. When the drive
is put into reset by setting the RESET line
to low, then the drive pulls CLOCK and DATA
line to low on its own.

The fact that we can see the CLOCK line
going low tells us that the input part of
the XA1541's CLOCK line is working fine. So
it must be the output part of the CLOCK line
that we should look further.

Drive-Detect:
Failed. Set clock to low, alter Atn - data and Atn should both change
state following Atn output. However, only Atn output changes state.
Data input remains high.

This is another indication for the CLOCK
output line not working as expected. The
drive doesn't "see" the CLOCK toggling and
therefore the EXOR gate is not triggered and
therefore the DATA line toggling is not
done.

Drive-detect-inv:
Failed. Only Atn changes state, Data remains high.

Same as above.

Drive-Detect-Combo:
Failed due to the same lack of ability to make Data react as described
above.

Yep, same as above.

Drive-Detect-Jitter:
Seems to work though Data doesn't react every time it should.

That's right and the reason, why the keyboard
repeat rate should be set to maximum.

Then I tried XCDETECT 0.18:

I'm omitting this report, because the results
above clearly tell that either your LPT port
or the XA1541 adaptor itself does not behave
as it should.

If you own a multimeter (a simple logic
tester _could_ work also), then please make
some checks for the CLOCK output trace, see
my XA1541 schematic [1]:

1. Connect the black cable of the
multimeter with GND, e.g. pin 18 of
the LPT port.

2. Test (using the red cable) pin 14 of
your LPT port with the XA1541 not
connected. Toggle the CLOCK line with
the XCTest utility and check that you
can see both voltage levels, a high
(2.8V...5V) as well as a low
(0V...0.8V).

3. Connect the XA1541 cable and do the
same test at pin 14, but "behind" the
XA1541's DB-25 connector.

4. Follow the trace of the CLOCK output
line beginning at pin 14 up to the
small SMD resistor. You should see the
line toggling at both side, before and
after the resistor.

5. Follow the trace from the resistor to
the small transistor. You should end
up at the left lead. Again check that
you can see both logic levels here,
when you toggle the CLOCK output line
with the help of XCTest.

6. Check the transistors output line which
is the middle lead at its opposite. Here
the logic levels should be inverted. It
may be that you need to connect an IEC
device first and switch it to on, so
that you can see a full high level.

7. Finally follow the trace from the
transistors output up to the IEC
connector and check that the line
toggling correctly ends up on the IEC
bus.


Womo

[1] http://d81.de/R.I.P/png/XAP1541V2-sch.png
.



Relevant Pages

  • Re: Capacitor Discharging with CMOS Gate
    ... tristate buffers that can gate a clock out to a connector on one of ... our VME modules. ... apply +3 dBm RF to the connector as an input, ... module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... tristate buffers that can gate a clock out to a connector on one of ... our VME modules. ... apply +3 dBm RF to the connector as an input, ... module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... one of my better customers started blowing up Tiny Logic ... tristate buffers that can gate a clock out to a connector on one of ... apply +3 dBm RF to the connector as an input, ... module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... John Larkin wrote: ... connector on one of our VME modules. ... your module and the customer is applying a 3dBm clock to it? ... with a JFET compound follower with hardwired 1MR pulldown from gate to gnd for a daisy chained drive, and a switchable 56R for proper relatively broadband termination as required. ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... John Larkin wrote: ... Logic tristate buffers that can gate a clock out to a ... connector on one of our VME modules. ... your module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)

Loading