Re: Mueller and Muller timing recovery

On Wed, 29 Apr 2009 13:33:24 -0700 (PDT), julius <juliusk@xxxxxxxxx>
wrote:
Forget the carrier, just do full-on baseband simulation.
And forget closing the feedback loop. Just look at
the output of your loop filter. Set the timing offset
to different values and see if the output of the loop
filter converges to something. See if this something
is proportional to your timing offset.

If I understand what you're suggesting correctly, the output will be a
constantly increasing phase difference wrapped around the symbol
period ie it will look like a saw-tooth shape because of the ever
increasing timing error between the transmit clock & receive clock
without being compensated by adjusting the sampling phase.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
.

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