Re: Real-time sinusoidal parameter estimation?

HardySpicer wrote:
On Oct 21, 2:41 pm, Tim Wescott <t...@xxxxxxxxxxxxxxxx> wrote:
alecwei wrote:
Hi folks,
I need to estimate the frequency and phase of a sinusoid in the presence
of noise with a fairly high accuracy. The algorithm will most likely be
implemented on an FPGA for a real-time control system. I have done some
research on the net and experimented with MATLAB a bit, and the only robust
solution (least-squares based) I came up with uses singular value
decomposition (SVD) of large matrices (hundreds x hundreds), which is
really impractical for an FPGA. My feeling is that anything that uses
matrix decomposition or inversion will probably be too complex in terms of
computation and resource usage. Could someone recommend an estimation
algorithm that is robust and practical at the same time? Let's assume the
number of samples to estimate from will be around 300. Thanks all!
How wide is the frequency range, how many cycles are in your 300
samples, how much noise, how predictable is the amplitude?

There are a lot of different ways you could do this, each one with it's
advantages and disadvantages, and better or worse fit to your problem.

For a moderately narrow frequency range and lots of cycles per sample
interval you could break your 300 samples into bunch of little one-cycle
sets at the nominal frequency, and estimate the phase of each set. Then
you can unwrap the phase and find the offset and slope of the
collection. This will _probably_ work OK for a +/- 10% variation in
frequency from nominal (I'd have to do some math to be sure).

Alternately, is there a reason you can't lock onto the signal with a
PLL? Once locked this would track frequency and phase in a predictable
manner, and would have the advantage of having IIR dynamics which are
both minimum phase and easier to model as part of a control system.

--

Tim Wescott
Wescott Design Serviceshttp://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details athttp://www.wescottdesign.com/actfes/actfes.html

A PLL has a lock range. Normally the free-running frequency of the VCO
defines the centre frequency and the frequency
varies up and down with respect to this (as in FM). He would need to
have a range of frequencies and set-up the PLL carefully at the
centre.
If you change the free-running frequency you need to change the loop
dynamics too.


Hardy

I think you're thinking analog PLLs. You have a lot more freedom to deal with the weirdness if you implement the PLL digitally.

But the OP needs to give us more detail.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details at http://www.wescottdesign.com/actfes/actfes.html
.

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