FIR filter optimization
- From: "chivak" <cd_prasad@xxxxxxxxxxx>
- Date: Wed, 30 Jul 2008 21:37:04 -0500
Hi All,
I would like to know the effectiveness of the canonic signed digit
algorithm (or any other algorithm that uses power of 2 coefficients for FIR
implementation like Reduced adder graph ) when the input data and
coefficient bit widths are large.
For example: i have a 25 tap symmetric Half band filter.
if a direct form filter is used, it will need 6 multiplies.
on the other hand, if i convert the rounded binary values of the
original coefficients to canonic signed digits, i can drastically reduce
the number of ones(adders).
My question is: Having reduced the number of adders, do we really get
siginificant hardware benefits using any of these optimised methods
when the bit widths are large(say 18 bit input data and 18-bit
coefficients).
The implementation approach i use is shift and add. My thinking is that
if the shift is large, then the adder width increases and depending on
the number of levels of adders, we may or may not achieve significant
savings. Am i correct? Any literature or suggestion this direction is
aprreciated.
-Regards,
Chivak
.
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