Re: Low freq to high freq conversion
- From: Tim Wescott <tim@xxxxxxxxxxxxxxxx>
- Date: Tue, 03 Jun 2008 16:23:30 -0700
Jerry Avins wrote:
markt wrote:The reference low frequency with 3 to 4 decimal places of precision canbeconsidered for this implementation. I am just trying to know the methodofimplementation.
Yeah, no problem... I think we got obsessed with precision because you
included so many digits.
Well, I've never gone UP to get to my output. Typically you have a
reference, say 10 MHz, and a VCO at a higher frequency that covers a range
of frequencies that includes your desired frequency. The for a PLL, the
reference and VCO are both divided DOWN to some comparison frequency, and
the phase delta (pulses in COTS parts) drives a charge pump whose output
is filtered and passed as the control voltage to the VCO.
I've gone up and closed a loop, but it was touchy. You only get one update on the oscillator frequency for each cycle of the reference. That means that if an error signal is needed to maintain the lock, there will be a sawtooth frequency modulation. I got RCA's Outstanding Achievement Award for making the sawtooth amplitude small enough.
Jerry
I'm not sure what you were working on, but many PLLs have a much higher oscillator frequency than the frequency of the phase comparator, and work fine.
Frequency synthesizers often have a 1- or 10-kHz reference, with tens or hundreds of MHz (or more!) oscillator frequency.
Genlocking a digital camera to NTSC video sync means going from 15kHz or so up to a 13 some-odd MHz pixel clock (if you're not going up to a higher pixel clock, or going up from the 30Hz frame rate).
Etc.
Note that these do require a stable oscillator locking to another stable oscillator -- but that may be just what the OP has.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details at http://www.wescottdesign.com/actfes/actfes.html
.
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