Re: PLL to generate low frequencies
- From: "Robert Lacoste" <use-contact-at-www-alciom-com-for-email>
- Date: Tue, 3 Jun 2008 17:12:35 +0200
"paryanz" <dr.asthana@xxxxxxxxx> a écrit dans le message de news:
puGdnXtMwJncg9jVnZ2dnUVZ_hOdnZ2d@xxxxxxxxxxxxxxx
Hi,
This is my first post to this forum. I have a reference oscillator of 12.7
MhZ, how do I generate the following frequencies using this oscillator
16.863406408094434 Hz
16.722408026755854
16.694490818030051
13.755158184319120
12.562814070351759
12.531328320802006
12.062726176115802
11.148272017837234
10.405827263267431
10.060362173038229
10.040160642570282
10.010010010010012
I would need roughly a 0.01Hz frequency resolution. Would a fractional PLL
be a solution to this problem.
Most of the papers I have read deal with increasing the output freq to
several Mhz or Ghz for implementing a PLL. But this implementation of mine
requires to reduce the generated freqs, I would appreciate any help advice
or some kind of code which would help me solve this problem.
Dear Aryan,
A direct digital synthetizer (DDS) would be far more suited to your problem
than a PLL. For example with a chip like the AD9832 (5$/1k budgetary price
on Analog's web site) and clocked with your 12.7MHz source you will get a 32
bit tuning word meaning a resolution better than 0.05Hz from DC to around
5MHz. And will require only 10mA. See www.analog.com/dds.
Friendly yours,
Robert Lacoste
www.alciom.com
.
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