Re: doubts in the design of FIR filter

On 29 Mai, 10:22, faz <fazulu.v...@xxxxxxxxx> wrote:
Dear all,

I have some doubts in the design of FIR filter...pls clarify

1.Can i set  the clock frequency of the FIR filter at any frequency i
want but pretty much higher than the sample rate?
  for example :Fc=3.5khz
                    Fs=8khz
         can i clock as any value >8khz say 1Mhz(considering the max
clock for target device)

This is a question on hardware, not FIR design. One does not
'set the clock frequency' of a FIR filter. One specifies the
sampling frequency of the system and works out the frequency
response from there.

If there is a restriction on the clock frequency wrt sampling
frequency, it will be determined by hardware considerations.

2.For 256 taps ..Which is the best FIR filter design method for lower
cut off frequncies say upto 100khz and for higher cut off frequency
range say from Mhz to Ghz??

The question doesn't make sense. Filters are designed in terms
of normalized frequency responses, not the number of coefficients
or frequency range.

3.Whether direct form non-symmetric filter structure can support
symmetric coefficients??whether the response computed is same as
symmetric filter structure??

Again, that's a hardware-specific question. I have no particular
knowledge about what is smart to do in hardware, but if a system
*requires* FIRs to be symmetric it will be because one wants so
save some area or memory on an IC by re-using internal data
or adders/multipliers.

There is no conceptual difference between symmetric and
non-symetric FIRs.

4.In addition to impulse test(basic test to check FIR filter
operation),step test,sine wave test.What are other test that has to be
compulsorily performed in time domain to check the proper working
filter operation before giving any arbitary input to the filter??

None in particular, that I can think of. You might want to
have a look at finite-word-length effects if you use fixed-
point arithmetics, but FIRs ought to be straightforward.

Rune
.

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