Re: Optimal FFT algorithm for hardware implementation ?
- From: ARH <haghdoost@xxxxxxxxx>
- Date: Wed, 7 May 2008 10:18:56 -0700 (PDT)
Hi Chris
Sorry for my late reply, I am new to FFT and DSP algorithms, so I try
to found more about CORDIC algorithm in wiki and I found that this
algorithm developed to calculate hyperbolic and trigonometric
functions no hardware multiplier is available but I have no limitation
in my design so I want to use multiplier for upgrading matrix
multiplication performance. Regarding to Quaternion I found no related
text in the net, I think it would be an extension of complex
numbers !
I think it would be better for me to forget optimize FFT algorithm,
because these algorithms have complexity which aren’t suitable for
starting a design. So I prefer to start with a very simple FFT
algorithm, would you mind help me to figure out this from jungle of
information in the net ?
Regards
ARH
On May 4, 4:21 pm, chris <chris.fel...@xxxxxxxxx> wrote:
The FFTW source code and design will be a good source but in general
for new hardware design it may not provide too much insight because
it
was designed to be an optimal FFT for current processors (ie Intel,
etc). There is an interesting forward in IEEE SP Magazine from the
last couple months that touches on the subject of the FFTW.
If you are experimenting with new hardware design you have much more
flexibility in your data flow, computation, etc. You will have to
balance resources, size, power consumption, etc. If you do some
searches you will find interesting implementation based on CORDIC,
Quaterion blocks, and others.
Good Luck.
.
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