Re: jitter calculation for ADC

Do phase noise and jitter represent the same thing but the first is in
frequency domain and the second is in time domain?

Sort of, but not necessarily. Jitter is derived from phase noise, but not
all of your phase noise is typically used to calculate jitter.
Low-frequency phase noise, for example, is generally assumed as drift, not
jitter, and high frequency phase noise (10s of MHz) probably won't impact
the calculation. 12 kHz - 20 MHz is an often used integration.

By reviewing the manuals I have, I found a clock skew of 150 ps! To me,
it
appears to be very high compared with what I am expecting from time
jitter.
Should I consider the clock skew as a worst case value for jitter.

NO! Skew is NOT jitter. Skew is typically the time difference between
separate output ports in a clock driver, and yes, it will be fixed for a
given part. It could also mean the delay between input and output, but
that's generally referred to as delay, not skew. Skew is important when
you're passing data from one part to another, or across clock boundaries in
the same part, each clocked with a separate output from some
clock-distribution scheme. For 125 MHz data, it is doubtful that a 150 ps
skew will cause much grief. If it does, you've probably got other timing
issues you need to resolve first.

Note, however, that various digital circuitry can add to your jitter
problem IF it is in-line before the input to your ADC clock. Good clock
drivers, e.g. ECL/PECL, can have sub-picosecond jitter specs. I would not
recommend using anything using TTL as a clock source if jitter is a major
concern. :)

Mark


.

Relevant Pages

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