Re: Demodulating AM pulse width coding (long post)

On Sat, 26 Apr 2008 16:18:29 -0700, rickman wrote:

I am decoding an IRIG-B signal in an FPGA. The signal is 100 bps
encoded with pulse width with three levels (0, 1, position identifier)
and modulated in AM on a 1 kHz carrier. The AM is typically 3:1
amplitude ratio between the mark and the space.

I am thinking about demodulating the AM by analyzing the carrier a
single cycle at a time, starting with the zero crossing point. Using
the samples from an ADC, the carrier amplitude will be measured using a
correlation to a cycle of a reference 1 kHz sine wave. I believe this
is the same thing as performing a DFT on the one bin of 1 kHz. The
resulting value is related to the amplitude of the carrier.

I did some simple simulations using excel to see what error is
introduced by a phase misalignment. I am sampling at 8 kHz, so the
initial phase mismatch will be +-22.5 degrees using a reference with the
first sample at 22.5 degrees. The sampling clock is not phase locked to
the input signal, but it will be crystal controlled. The phase mismatch
resulted in a relatively low amplitude error (1.08 between the highest
and lowest). Adding in -6 dB of randomly distributed noise, the
measured amplitude for a cycle ranges over a ratio of 1.5 most of the
time. Given the 3x modulation factor, this seems adequate.

To allow for the difference in clock speed, at the end of each cycle of
the carrier, the correlator will resync to the positive going zero
crossing. This will require that I keep the last sample of the previous
cycle because it may also be the first sample of the next cycle if the
zero has just been crossed.

I plan to set the threshold of the level detector using a low pass
filter of the form Y1 = (1-a)Yi-1 + aXi. I will set 'a' so that it
takes some 1000 cycles to make a 10% movement of the mean. I expect I
will need to scale Y to compensate for the fact that the modulated pulse
width is not 50/50 duty cycle on the average. The 0 pulse is 2 cycles
of high AM and 8 cycles of low AM. The 1 pulse is 5 cycles of high AM
and 5 of low AM. The position identifier pulse (first of frame and last
of each 10 pulses) is 8 cycles of high AM and 2 low AM.

The pulse width will be decoded by counting the number of high and low
cycles. There will be some accounting for single cycle errors, e.g. if
the pattern over 10 cycles is 2 high, 1 low, 2 high and 5 low, this will
be decoded as a 1 and not a 0. I see this as a digital match, similar
to the analog correlation. Each series of 10 cycles will be XORed with
three reference patterns (0, 1, ref) producing three numerical results.
The highest one is considered the match.

I think this will provide a robust demodulation along with a good decode
of the pulse width and also preserve exact timing (to the ADC sample) of
the zero crossing which is the exact time reference.

Does anyone see a problem with this? Is any part of this overly
complicated?

One area I am not sure about is the low pass filter on the detector. A
single message is a second long. The average amplitude will vary message
by message. I would like the threshold to adjust very slowly once it is
"in the range" so that it does not wander much from message to message.
But this might result in a filter that will take many seconds to
initially lock in.

Is it uncommon to design a filter that adjusts more quickly with larger
errors and more slowly when the current output is near the next output?
Since the input samples range over a wide +- range by design, I am not
certain how I might do this.

I can see a lot of different approaches to this problem, and which one is
'best' depends greatly on your circumstances. I don't think your
approach is bad in itself, but it may be overly complicated and it will
only work well in a low-noise environment (in particular I suspect that
your synchronization method is weak).

You may find it more useful to only filter the values of '1' pulses, and
set your threshold to 2/3 the '1' level. This will make your filter
fairly immune to the distribution of ones and zeros within a message, and
should give you a more consistent threshold once it has latched on to the
right threshold value. If that algorithm gets confused by too many
zeros, then consider using a pair of envelope detectors to separately
track the '1' and '0' levels, and set your threshold between them.

Tracking the carrier phase with a PLL will make the system much more
robust to noise (zero crossing methods tend to enhance noise), assuming
that the carrier phase doesn't change much with time. Ditto tracking the
data timing with a PLL. If you track both sets of timing with PLLs then
you can make a nice set of three matched filters to the three data
symbols, and get yourself a near-optimal demodulator in the presence of
noise.

If acquisition time is important and you have processing power to throw
at the problem you can sample the data a second (or two or three) in
advance and process it in advance for the synchronization information,
then process it again to extract the data. This would give you about the
same performance as my PLL suggestion above, but it'd give you just as
good of reception of the very first message as all the rest of them
(assuming all but the noisiest of environments).

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html
.

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