Re: Demodulating QPSK

I have a general-purpose PLL implemented as a primitive in a language where I can easily run signals through it, plot the outputs, and tweak its parameters: initial frequency, loop gain, loop bandwidth and I/Q filter bandwidth. All signal processing is done with double precision floating point arithmetic and trig functions are computed using the C-RTL (not interpolated from table look-up), so I think we can pretty much rule out issues with overflow, quantization, etc. Can someone help me understand what I'm observing here?

Part I:
=======

I have as set of three test files. These files are totally synthetic (created digitally using the same language, no noise, etc.). They are described below.

File1: A 550 Hz. sine segment sampled at 48000 Hz. lasting 10 seconds followed by 10 seconds of the negative of the same sine (180-degree phase shift).

File2: A 550 Hz. cosine segment sampled at 48000 Hz. lasting 2 seconds followed by a 550 Hz. sine segment lasting two seconds followed by the negative of the previous cosine segment followed by the negative of the previous sine segment followed by the original cosine segment.

File3: A [cos]=[sin]=[-cos]=[-sin] segment repeated many times (totalling 10 seconds). Each (cos) or (sin) segment has a frequency of 550 Hz. and a duration of (4/300) seconds.

I deliberately set the inital frequency of the PLL to 555 Hz. so I could observe its lock-up behavior. When I process File1 through the PLL and observe the control frequency being fed back to the VFO (this would be the locked frequency), I see a brief transient while the loop acquires lock. Thereafter, the locked frequency remains steady as a rock on 550 Hz. until the phase changes. Then there is another brief transient while the loop re-acquires lock and then the locked frequency remains steady as a rock on 550 Hz. through the remainder of the file.

When I process File2 through the PLL and observe the control frequency, the behavior is similar. At the beginning of each segment there is a brief frequency transient after which the loop locks and remains steady until the next phase change.

When I process File3 through the PLL, there is a brief transient at the beginning of the file and then the loop locks and the control frequency remains steady. The problem is that the loop locks on a frequency that is decidedly different from 550 Hz. (say 562.5 Hz. or 547 Hz., depending on the setting of the loop bandwidth or the type of loop filter).

Part II:
========

I raise each sample of File1, File2, and File3 to the fourth power and run each file through a FIR bandpass filter with cutoff frequencies of 2000 Hz. and 2400 Hz. to yield File1a, File2a, and File3a respectively.

I observe that the spectra of File1 and File2 are sharply peaked at 2200 Hz. and the spectrum of File3 is somewhat diffuse with the component at 2200 Hz. being about 30 dB below its nearest neighbors.

If I run these files through the PLL, File1 and File2 lock up (as expected) at 2200 Hz. with no transients at the times of phase change. However, File3a locks up at some frequency other than 2200 Hz. (and I think that frequency is about 4 times the lock-up frequency of File3).

I'm sure there's a reasonable explanation for what I'm observing. I was thinking that the weird lockup frequency was related to the time-constant of the loop filter, but radically changing the time-constant of the loop filter doesn't have much effect on the observed behavior. In particular, it seems to lock up on the same weird frequency no matter how I set the loop bandwidth.

.

Relevant Pages

  • Re: Demodulating QPSK
    ... loop bandwidth and I/Q filter bandwidth. ... so I could observe its lock-up behavior. ... brief transient while the loop acquires lock. ... the loop bandwidth or the type of loop filter). ...
    (comp.dsp)
  • Re: FSK Radio design
    ... I would set the PLL at the carrier frequency and pick off the VCO ... locked loop has to have a loop bandwidth appreciably wider than 1MHz ... the phase error will be far from zero. ...
    (sci.electronics.design)
  • Re: FSK Radio design
    ... I would set the PLL at the carrier frequency and pick off the VCO ... locked loop has to have a loop bandwidth appreciably wider than 1MHz ... any PLL above first order is going to zero out the static phase error. ...
    (sci.electronics.design)
  • Re: FSK Radio design
    ... I would set the PLL at the carrier frequency and pick off the VCO ... locked loop has to have a loop bandwidth appreciably wider than 1MHz ... the phase error will be far from zero. ...
    (sci.electronics.design)
  • Re: [PATCH 1/2] misc: add CARMA DATA-FPGA Access Driver
    ... the buffer has already been removed from the list. ... I thought it would be clearer to reviewers if I always used the lock to ... locks should protect wehat needs to be protected. ... You should note that it is only possible to exit the loop with the lock ...
    (Linux-Kernel)