Re: DSP Implementation Woes

On Jan 31, 8:36 am, brendan_onl...@xxxxxxxxxxx wrote:
Hi Ben,

I was *told* that this chip supports several discrete clock
frequencies....namely 8,16,24,32,44.1,96 KHz, and it doesn't use a Low-
pass interpolation/reconstruction filter at the lower clock
frequencies.

I think the chip must be using some form of low pass interpolation/
reconstruction filter at the lower clock frequencies. Do you mean 'in
addition to a ZOH'? A ZOH can be thought of as a rudimentary low
pass reconstruction filter.

My problems are occurring at 8KHz. The 'modulation'
envelope is having an effect when trying to reconstruct a sinusoid at
about 3.4KHz. It's not too dissatisfactory at this point, but by 3.6+
KHz there is alot of harmonic distortion from what I desire.

If the chip was using simply a ZOH with a 'steplength' of 1/8000
seconds,
the output would look distinctly un-sinusoidal at anything much above
1kHz.


In fact, at 8KHz the reconstruction looks of zero-order-hold type.


At 8kHz are you seeing 8000 ZOH steps per second or are you, by any
chance, seeing 8000n ZOH steps per second, where n is equal to
(perhaps) 8 or 10?
As pointed out earlier, the reconstruction filter must have a sharp
cut-off and should have significant attenuation at half the sampling
rate if
frequencies just below half the sampling rate are to be generated.
The reconstruction filter in your DAC may well be implemented
as an FIR operating at n-times the sample rate you are concerned with
and
with a ZOH output (at n-times your sample rate). Input to the FIR (at
n-times your sample rate) could be your samples padded with (n-1) zero
values between each one.
Try writing a data sequence in which only every (say) 100th
value is non-zero to the DAC and you will get an idea of the impulse
response
of the reconstruction filter - it may well be the sort of truncated
(windowed) sinc
shape that is typical of a low pass FIR. And it may be made up of ZOH
steps
at n-times your sampling rate.
Such an FIR low pass reconstruction filter _could_ be designed to have
very
significant attenuation at half the sampling rate but would then also
attenuate
frequencies just below half the sampling rate - in your example that
would mean
that by 3.6+ kHz there might be very little output at all from the
DAC. Some audio
codecs are designed so that the FIR reconstruction filter response is
down
only 6dB at half the sampling rate. (Does the datasheet for your DAC
give the
magnitude frequency response of the reconstruction filter?)
Running at a sampling rate of 44.1kHz, the effect you describe will be
present
for frequencies of 20+ kHz but in practical situations may not matter
because
other components in a 'CD-quality' audio system may have low pass
characteristics that mask the aliasing close to 22.05kHz.

So when I said 'push the chip', I simply meant to clock it up to 96KHz
and see if the signal fidelity of a discrete sinusoid at a discrete
frequency of about 0.8pi is any better.


What did you find?

Regards,

Donald

Thanks again,
Brendan

.

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