Re: DSP Implementation Woes

Hi Ben,

I was *told* that this chip supports several discrete clock
frequencies....namely 8,16,24,32,44.1,96 KHz, and it doesn't use a Low-
pass interpolation/reconstruction filter at the lower clock
frequencies. My problems are occurring at 8KHz. The 'modulation'
envelope is having an effect when trying to reconstruct a sinusoid at
about 3.4KHz. It's not too dissatisfactory at this point, but by 3.6+
KHz there is alot of harmonic distortion from what I desire.

In fact, at 8KHz the reconstruction looks of zero-order-hold type.

So when I said 'push the chip', I simply meant to clock it up to 96KHz
and see if the signal fidelity of a discrete sinusoid at a discrete
frequency of about 0.8pi is any better.

Thanks again,
Brendan




.

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