Re: How to calculate the RMS jitter for this OXCO?
- From: Allan Herriman <allanherriman@xxxxxxxxxxx>
- Date: Wed, 26 Dec 2007 14:26:28 +1100
On Tue, 25 Dec 2007 08:29:04 -0800 (PST), fl <rxjwg98@xxxxxxxxx>
wrote:
Hi,
I have the phase nosie specification of an OXCO at 10 MHz as:
Phase Noise
-90 dBc/Hz 1Hz
-120 dBc/Hz 10Hz
-135 dBc/Hz 100Hz
-140 dBc/Hz 1kHz
-140 dBc/Hz >10kHz
I want to get the jitter value in the normal UI unit. How to get that?
Thanks in advance.
Short answer:
In some ways, this is very easy to calculate. Just google for phase
noise to jitter calculator and plug the numbers in.
I used this one: http://www.jittertime.com/resources/pncalc.shtml
Long answer:
However, the results you get may or may not make sense.
Most of the jitter comes from the segments 1Hz - 10Hz (about 500ps
RMS) and the >1kHz segments, (e.g. 1kHz - 10kHz : 213ps RMS; 10kHz -
100kHz: 675ps RMS; 100kHz - 1MHz: 2.13ns RMS). Thus is it important
to set the limits of integration correctly.
0Hz - 1MHz: infinite jitter (the integration doesn't converge).
1Hz - 1MHz: 2.3ns RMS.
10Hz - 10kHz: 230ps RMS, one tenth of the 1Hz - 1MHz value.
Your application will tend to ignore noise above some frequency (known
as the noise bandwidth), possibly because of a bandpass filter, or
perhaps because this OCXO is being used as the reference for a PLL. In
that case, you need to set the upper limit of the integration at the
noise bandwidth of the PLL. The noise bandwidth will be roughly the
same as the -3dB bandwidth if you don't want to work it out exactly.
Similarly, your application may or may not be sensitive to low
frequency jitter, and you should set the lower limit of integration to
suit. For example, your oscillator may be timing a signal that is
later processed by a CDR (Clock and Data Recovery circuit). This
might be an optical or radio link or something like that. The CDR
will have a bandwidth, and it will tend to track jitter below that
bandwidth, and this low frequecy jitter won't contribute to eye
closure. Above that bandwidth, the jitter won't be tracked, and will
contribute to eye closure.
When calculating the total jitter, you should set the lower limit of
integration to the bandwidth of the CDR.
I guess I'm saying that you have to understand your application before
you you can perform this calculation and get answers that actually
mean something.
I find it interesting to ponder the sources of the phase noise.
Above 1kHz, the phase noise is "flat", i.e. 0dB / decade.
It's a pretty sure bet that there's a wideband noise floor of
-140dBc/Hz, which comes from the AWGN caused by the output amplifier.
It would be fair to assume that this continues out to offsets much
greater than 10kHz (hence the ">10kHz" number in your table).
Between 10Hz and 1Hz, the phase noise rises at 30dB / decade. I
assume that this is flicker noise (1/f, i.e. 10dB/decade) that
modulates the frequency of the oscillator (which gives the other
20dB/decade).
Back to c.a.f: A brickbat at the Altera people, who specify the
bandwidth of their PLL and SERDES components as "low", "medium" and
"high". How are we supposed to turn that into an actual frequency
that we can plug into a calculation? I understand that most engineers
wouldn't have a clue, and thus not quoting numbers reduces the support
overhead, but really, what were you thinking?
Regards,
Allan
.
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