Re: QPSK carrier recovery with multiply filter divide circuit

stenasc@xxxxxxxxx wrote:
Hi,

Has anyone ever got this method of coherent carrier recovery to work
correctly. I tried to implement it some time ago in an FPGA, but ran
into problems. Was put onto a different project, but now I might have
to look at this again. I know the Costas loop in another approach, but
the following was something I was able to put togrther quite quickly..

Here is what I have done to test it so far...

I have a 1MHz input signal which I multiply by 4 and then bandpass
filter at 4 Mhz to get rid of any other harmonics. This seems to work
fine. The sample rate is 16 Mhz and I am getting a triangular shape
waveform of freq 4 Mhz.

Now to divide it down the 4 Mhz down to 1Mhz. What is the best way...
use a PLL?

Here is what i think you would do....please criticise...I won't be
offended....

In order to get the frequency down does one multiply the 4 Mhz out of
the band pass filter with a 3 Mhz signal...(This multiplier would be
the phase detector in the PLL) The difference and sum frequencies
would be 1 Mhz and 7 Mhz. Using a first order LP filter in the PLL, I
should be able to get rid of the 7 Mhz signal and leave the desired 1
Mhz....does this sound correct?

I'll leave it at that for the present. It is getting late and I know
I'll have further questions based on any answers I get to the above.

Square up the 4 MHz signal with a clipper and use a cross-connected pair of D-type flip-flops to divide by 4. The Q and ~Q outputs will give you four phases to choose from.

Jerry
--
Engineering is the art of making what you want from things you can get.
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