Re: Undersampling: Specifying Clock Jitter?


John wrote:
On Jun 22, 3:36 pm, Phil <philguilleme...@xxxxxxxxxxxxxxxxxxx> wrote:
Hi all,

I'm basically trying to design a power spectrum analyser that can
capture channels with a bandwidth of 100 MHz. I select either 10 MHz
- 110 Mhz or 135 MHz - 235 MHz and am sampling with a 250 MHz ADC.
The ADC has a full power bandwidth of 1 GHz and has 12 bits.
My goal is to be able to detect a signal that is 55 dB lower than
another signal that is 500 kHz away. I also want to reduce the amount
of false detection.

Assuming that I choose a sufficiently large FFT and that I am
windowing properly, how should I specify the phase noise (jitter) for
the sampling clock such that it does not limit my performance and at
the same time is not over designed.

Based on the analog devices appnote, AN-756,http://www.analog.com/UploadedFiles/Application_Notes/593845726044367...
I think that for my purpose, I should specify the phase noise from 100
kHz to 1 GHz. Is this correct?

Apart from this appnote and a couple other small articles, I am having
difficulty at locating good references explaining how to spec the
sampling clock and what to use for integration bandwidth when
determining jitter.

Thanks for any help.

BR,
Phil

For detection at 500 kHz offset you need to integrate the phase noise
PSD over 500 kHz +/- W/2, where W is the BW of the signal to be
detected. The integrated result should be 55 dBc + desired SNR.

John

If I understand correctly, I should set my upper integration limit of
my spec to the maximum bandwidth that I a signal is likely to have.
Is this correct?

If I were to assume for now that the phase noise PSD for f>500 kHz is
flat, should I then add margin of 3*log2(1GHz/125MHz) to my spec to
take into account the aliasing that will occur due to my 1GHz full
power bandwidth?

Thanks again.

Phil

.

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