interface between two different rate modules




hello everyone

in my project i had to make a slicer that would produce
output at every clock but the next module(depuncture) product output
for valid inputs at two clock for three clocks...

i mean the dpeuncture modules takes 1 "x1,y1" pair at time t=1 and moves
it forward
as it is(no puncturing required) now it recieves a input pair"x2,y2" at
time t=2 but the output for this part will be generated for two clocks
(i.e x2,null(symbol) at t=2,and null,y2 at t=3).in this way the unit
producing the punctured data produces a puncutred data "P" for two clocks
while depuncutre unbit produces depuncutred data for puncutred data "P"
for three clocks....this way two of the modules give the complete valid
outputs at different number of clock(i.e puncutrer takes two clock while
depuncturer takes three clocks)i hope i have explained my scenario.....

is there any way that depuctured data could produce valid output without
the source producing the punctured data to wait......please note that i am
doing it in FPGA so keep it in mind...a general solution will be helpful as
well

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