Re: McASP Initialisation on C6713

And this are my configs:

/* global registers */

MCASP_ConfigGbl cfgMCASPGBL = {

/* pin function register */

MCASP_PFUNC_RMK( MCASP_PFUNC_AFSR_MCASP, /* McASP function */

MCASP_PFUNC_AHCLKR_MCASP, /* McASP function */

MCASP_PFUNC_ACLKR_MCASP, /* McASP function */

MCASP_PFUNC_AFSX_MCASP, /* McASP function */

MCASP_PFUNC_AHCLKX_MCASP, /* McASP function */

MCASP_PFUNC_ACLKX_MCASP, /* McASP function */

MCASP_PFUNC_AMUTE_MCASP, /* McASP function */

MCASP_PFUNC_AXR7_MCASP, /* McASP function */

MCASP_PFUNC_AXR6_MCASP, /* McASP function */

MCASP_PFUNC_AXR5_MCASP, /* McASP function */

MCASP_PFUNC_AXR4_GPIO, /* GPIO function: Timer1: TOUT1 */

MCASP_PFUNC_AXR3_MCASP, /* McASP function */

MCASP_PFUNC_AXR2_MCASP, /* McASP function */

MCASP_PFUNC_AXR1_MCASP, /* McASP function */

MCASP_PFUNC_AXR0_MCASP /* McASP function */

),

/* pin direction register */

MCASP_PDIR_RMK( MCASP_PDIR_AFSR_DEFAULT, /* Input: None */

MCASP_PDIR_AHCLKR_IN, /* Input: AUX-CLK */

MCASP_PDIR_ACLKR_DEFAULT, /* Input: None */

MCASP_PDIR_AFSX_OUT, /* Output: LRCLK */

MCASP_PDIR_AHCLKX_IN, /* Input: AUX-CLK */

MCASP_PDIR_ACLKX_OUT, /* Output: BCLK */

MCASP_PDIR_AMUTE_DEFAULT, /* Input: None */

MCASP_PDIR_AXR7_OUT, /* Output: H_DATA_OUT */

MCASP_PDIR_AXR6_OUT, /* Output: D_DATA_OUT */

MCASP_PDIR_AXR5_OUT, /* Input: A_DATA_OUT */

MCASP_PDIR_AXR4_OUT, /* Output: Timer1 */

MCASP_PDIR_AXR3_IN, /* Input: D_DATA_IN2 */

MCASP_PDIR_AXR2_IN, /* Input: D_DATA_IN */

MCASP_PDIR_AXR1_IN, /* Input: A_DATA_IN2 */

MCASP_PDIR_AXR0_IN /* Input: A_DATA_IN */

),

/* DIT mode control register */

MCASP_DITCTL_RMK( MCASP_DITCTL_VB_ZERO, /* valid bit for odd time
slots (right subframe) */

MCASP_DITCTL_VA_ZERO, /* valid bit for even time slots (left
subframe) */

MCASP_DITCTL_DITEN_TDM /* TDM or Burst mode */

),

/* digital loopback control register */

/* output of the transmit serializers is connected internally to the
in put of the receive serializers. */

/* Therefore you can check the receive data against the transmit
data */

MCASP_DLBCTL_RMK( MCASP_DLBCTL_MODE_DEFAULT, /* loopback generator
mode */

MCASP_DLBCTL_ORD_DEFAULT, /* loopback order */

MCASP_DLBCTL_DLBEN_DISABLE /* loopback disabled */

),

/* audio mute control register */

MCASP_AMUTE_RMK( MCASP_AMUTE_XDMAERR_DISABLE, /* transmit DMA
error */

MCASP_AMUTE_RDMAERR_DISABLE, /* receive DMA error */

MCASP_AMUTE_XCKFAIL_DISABLE, /* transmit clock failure */

MCASP_AMUTE_RCKFAIL_DISABLE, /* receive clock failure */

MCASP_AMUTE_XSYNCERR_DISABLE, /* unexpected transmit frame synx
error */

MCASP_AMUTE_RSYNCERR_DISABLE, /* unexpected receive frame synx
error */

MCASP_AMUTE_XUNDRN_DISABLE, /* transmiter underrun error */

MCASP_AMUTE_ROVRN_DISABLE, /* receiver overrun error */

MCASP_AMUTE_INEN_DISABLE, /* AMUTEIN is ignored by AMUTE */

MCASP_AMUTE_MUTEN_DISABLE /* AMUTE pin disabled */

)

};



/* receive registers */

MCASP_ConfigRcv cfgMCASPRCV = {

/* receive format unit bit mask register */

0x00FFFFFF, /* masked with value of rpad,rpbit in rfmt */

/* receive bit stream format register */

MCASP_RFMT_RMK( MCASP_RFMT_RDATDLY_0BIT, /* receive bit
delay */

MCASP_RFMT_RRVRS_MSBFIRST, /* bitsream is MSB first */

MCASP_RFMT_RPAD_RPBIT, /* pad extra bits with one specified by
RPBIT */

MCASP_RFMT_RPBIT_OF(0x17), /* use bit 23 to pad extra
bits */

MCASP_RFMT_RSSZ_32BITS, /* slot size ist 32 bits */

MCASP_RFMT_RBUSEL_DAT, /* reads from XRBUF[n] originate on
configuration bus */

MCASP_RFMT_RROT_8BITS /* rotate rigth by 8 bit
positions */

),

/* receive frame sync control register (LRCLK) */

MCASP_AFSRCTL_RMK( MCASP_AFSRCTL_RMOD_OF(0x02), /* 2-slot TDM (of
32) */

MCASP_AFSRCTL_FRWID_WORD, /* single word */

MCASP_AFSRCTL_FSRM_INTERNAL, /* internally generated receive
frame sync */

MCASP_AFSRCTL_FSRP_ACTIVEHIGH /* rising edge indicates the
beginning of frame */

),

/* receive clock control register (BCLK) */

/* if receive and transmit transmissions are synchron, this register
is irrelevant */

MCASP_ACLKRCTL_RMK( MCASP_ACLKRCTL_CLKRP_RISING, /* sample at rising
edge of the serial clock */

MCASP_ACLKRCTL_CLKRM_EXTERNAL, /* external receive clock
source: AHCLKR */

MCASP_ACLKRCTL_CLKRDIV_OF(0x01) /* divide receive clock by 2
(BCLK: 12,288) */

),

/* receive high-frequency clock control register (MCLK) */

MCASP_AHCLKRCTL_RMK(MCASP_AHCLKRCTL_HCLKRM_EXTERNAL, /* external clock
from AHCLKR */

MCASP_AHCLKRCTL_HCLKRP_RISING, /* rising edge */

MCASP_AHCLKRCTL_HCLKRDIV_OF(0x01) /* divide receive clock by 2
(BCLK: 12,288) */

),

/* receive TDM slot register */

0x00000003, /* TDM time slot 0,1 active */

/* receiver interrupt control register */

MCASP_RINTCTL_RMK( MCASP_RINTCTL_RSTAFRM_DISABLE, /* receive start of
frame... */

MCASP_RINTCTL_RDATA_DISABLE, /* receive data ready... */

MCASP_RINTCTL_RLAST_DISABLE, /* receive last slot... */

MCASP_RINTCTL_RDMAERR_DISABLE, /* receive DMA
error... */

MCASP_RINTCTL_RCKFAIL_DISABLE, /* receive clock
failure... */

MCASP_RINTCTL_RSYNCERR_DISABLE, /* unexpected receive frame
sync... */

MCASP_RINTCTL_ROVRN_DISABLE /* receiver overrun... */

/* interrupt does generate a McASP receive interrupt */

),

/* receive clock check control register */

MCASP_RCLKCHK_RMK( MCASP_RCLKCHK_RCNT_DEFAULT, /* */

MCASP_RCLKCHK_RMAX_OF(128), /* */

MCASP_RCLKCHK_RMIN_OF(127), /* */

MCASP_RCLKCHK_RPS_DIVBY1 /* check prescaler */

)

};



/* transmit registers */

MCASP_ConfigXmt cfgMCASPXMT = {

/* transmit format unit bit mask register */

0x00FFFFFF, /* masked with value of xpad,xpbit in xfmt */

/* transmit bit stream format register */

MCASP_XFMT_RMK( MCASP_XFMT_XDATDLY_0BIT, /* receive bit
delay */

MCASP_XFMT_XRVRS_MSBFIRST, /* bitsream is MSB first */

MCASP_XFMT_XPAD_ZERO, /* pad extra bits with zero */

MCASP_XFMT_XPBIT_OF(0x00), /* pad extra bits with zero */

MCASP_XFMT_XSSZ_32BITS, /* slot size ist 32 bits */

MCASP_XFMT_XBUSEL_DAT, /* writes to XRBUF[n] originate from
configuration bus */

MCASP_XFMT_XROT_24BITS /* rotate rigth by 24 bit
positions */

),

/* transmit frame sync control register (LRCLK) */

MCASP_AFSXCTL_RMK( MCASP_AFSXCTL_XMOD_OF(0x02), /* 2-slot TDM (of
32) */

MCASP_AFSXCTL_FXWID_WORD, /* single word */

MCASP_AFSXCTL_FSXM_INTERNAL, /* internally generated transmit
frame sync */

MCASP_AFSXCTL_FSXP_ACTIVEHIGH /* falling edge indicates the
beginning of frame */

),

/* transmit clock control register (BCLK) */

MCASP_ACLKXCTL_RMK( MCASP_ACLKXCTL_CLKXP_FALLING, /* sample at falling
edge of the serial clock */

MCASP_ACLKXCTL_ASYNC_SYNC, /* synchronous clock for transmit and
receive */

MCASP_ACLKXCTL_CLKXM_INTERNAL, /* external transmit clock
source: AHCLKX */

MCASP_ACLKXCTL_CLKXDIV_OF(0x01) /* divide transmit clock by 2
(BCLK: 12,288) */

),

/* transmit high-frequency clock control register (MCLK) */

MCASP_AHCLKXCTL_RMK(MCASP_AHCLKXCTL_HCLKXM_EXTERNAL, /* external clock
from AHCLKX */

MCASP_AHCLKXCTL_HCLKXP_RISING, /* rising edge */

MCASP_AHCLKXCTL_HCLKXDIV_OF(0x01) /* divide transmit clock by 2
(BCLK: 12,288) */

),

/* transmit TDM slot register */

0x00000003, /* TDM time slot 0,1 active */

/* transmit interrupt control register */

MCASP_XINTCTL_RMK( MCASP_XINTCTL_XSTAFRM_DISABLE, /* transmit start of
frame... */

MCASP_XINTCTL_XDATA_DISABLE, /* transmit data
ready... */

MCASP_XINTCTL_XLAST_DISABLE, /* transmit last slot... */

MCASP_XINTCTL_XDMAERR_DISABLE, /* transmit DMA
error... */

MCASP_XINTCTL_XCKFAIL_DISABLE, /* transmit clock
failure... */

MCASP_XINTCTL_XSYNCERR_DISABLE, /* unexpected transmit frame
sync... */

MCASP_XINTCTL_XUNDRN_DISABLE /* transmit overrun... */

/* interrupt does generate a McASP transmit
interrupt */

),

/* transmit clock check control register */

MCASP_XCLKCHK_RMK( MCASP_XCLKCHK_XCNT_DEFAULT, /* */

MCASP_XCLKCHK_XMAX_OF(128), /* */

MCASP_XCLKCHK_XMIN_OF(127), /* */

MCASP_XCLKCHK_XCKFAILSW_DISABLE,/* transmit clock failure
detect */

MCASP_XCLKCHK_XPS_DIVBY1 /* check prescaler */

)

};



/* serial control registers */

MCASP_ConfigSrctl cfgMCASPSRCTL = {

/* serializer control register 0 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_RCV /* serializer is receiver */

),

/* serializer control register 1 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_RCV /* serializer is receiver */

),

/* serializer control register 2 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_RCV /* serializer is receiver */

),

/* serializer control register 3 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_RCV /* serializer is transmitter */

),

/* serializer control register 4 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_DEFAULT, /* drive on pin
logic */

MCASP_SRCTL_SRMOD_INACTIVE /* serializer is disabled */

),

/* serializer control register 5 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_XMT /* serializer is disabled */

),

/* serializer control register 6 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_XMT /* serializer is transmitter */

),

/* serializer control register 7 */

MCASP_SRCTL_RMK( MCASP_SRCTL_DISMOD_LOW, /* drive on pin logic */

MCASP_SRCTL_SRMOD_XMT /* serializer is transmitter */

)

};



_____________________________________
Do you know a company who employs DSP engineers?
Is it already listed at http://dsprelated.com/employers.php ?
.