Re: Digital PLL acquisition problem
- From: Tim Wescott <tim@xxxxxxxxxxxxxxxx>
- Date: Fri, 16 Mar 2007 08:43:55 -0700
Vladimir Vassilevsky wrote:
Unless you're trying to lock to a signal that's embedded in noise, in which case a state machine detector will be worse than useless.
patrick.melet@xxxxxxxxxxxxx wrote:
I made a digital PLL, with multiplier based phase detector, digital
loop filter C1 + C2/(1-z^-1) and a digital NCO with 16 bits
accumulator
I want to lock on a 22170 Hz sine signal in 10 ms lock time
My problem is when I don't have the 22170 Hz signal, my output filter
sweep very slowly (1 second) beetween min and max of my input NCO and
don't lock when my 22170 Hz signal is on
So I put a window at the ouput of my filter to only sweep in a 2600 Hz
window
And when this ouput is out of this window I reset the filter
accumulator to its maximum value, now the ouput of the filter sweep
this window very slowly ( about 2 seconds)
So with this when I put my 22170 Hz off and on my loop locks into it,
but I have a very long lock time ( 200 ms) and not 10 ms...
Is in acquisition mode I have to "manually" sweep my input NCO in the
2600 Hz window and look at the ouput of the loop filter to say if I'm
lock or not ?
1. You should use the state machine frequency/phase detector, not a multiplier. This will guarantee the reliable quick PLL pull-in.
If you sample the data first, then implement your PLL, a pure-logic state machine frequency/phase detector will have an uncertainty around the edges of +/- 1/2 sample, which quite broad for many purposes. I rarely encounter an application that can suffer this much noise being injected by the algorithm itself.
Assuming that the tone is strong enough you can get the same effect by estimating the incoming signal's phase and counting rotations -- this works very well in practice, with much noisier signals than you can hope to use a frequency/phase detector on, and doesn't have the edge uncertainty. It does have the drawback that it twists your brain in loops, but once you get it figured out you'll be smarter than you were going in.
2. The pull-in time depends on the loop filter parameters. There is a tradeoff between the PLL noise bandwidth and the pull-in time.Yea verily. If you can detect lock you can switch (or slide) to a narrower bandwidth once the phase & frequency are acquired.
3. The RMS variation of the NCO frequency can be used as the measure of PLL lock.
Assuming a pure enough tone -- here again, in a noisy environment it can be rough to distinguish noise-induced RMS variation of the error signal from an unlocked loop. If you're doing something extreme like digging a tone that's buried several dB deep into the noise then you can have a perfectly adequate lock yet have a very difficult time pulling it out -- in this case you'd have to low-pass filter the NCO frequency variations, and look at the RMS variation of the resulting signal. It could be done, but you'd have to approach the problem of determining when you have a good lock very carefully lest you simply build a false-positive generator.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Posting from Google? See http://cfaj.freeshell.org/google/
"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html
.
- Follow-Ups:
- Re: Digital PLL acquisition problem
- From: Vladimir Vassilevsky
- Re: Digital PLL acquisition problem
- References:
- Digital PLL acquisition problem
- From: patrick . melet
- Re: Digital PLL acquisition problem
- From: Vladimir Vassilevsky
- Digital PLL acquisition problem
- Prev by Date: Re: PID controller with second derivative?
- Next by Date: Re: Digital PLL acquisition problem
- Previous by thread: Re: Digital PLL acquisition problem
- Next by thread: Re: Digital PLL acquisition problem
- Index(es):
Relevant Pages
|
