Re: Digital PLL acquisition problem

On Mar 16, 4:46 am, patrick.me...@xxxxxxxxxxxxx wrote:
Hi all,

I made a digital PLL, with multiplier based phase detector, digital
loop filter C1 + C2/(1-z^-1) and a digital NCO with 16 bits
accumulator

I want to lock on a 22170 Hz sine signal in 10 ms lock time

My problem is when I don't have the 22170 Hz signal, my output filter
sweep very slowly (1 second) beetween min and max of my input NCO and
don't lock when my 22170 Hz signal is on

So I put a window at the ouput of my filter to only sweep in a 2600 Hz
window
And when this ouput is out of this window I reset the filter
accumulator to its maximum value, now the ouput of the filter sweep
this window very slowly ( about 2 seconds)

So with this when I put my 22170 Hz off and on my loop locks into it,
but I have a very long lock time ( 200 ms) and not 10 ms...

Is in acquisition mode I have to "manually" sweep my input NCO in the
2600 Hz window and look at the ouput of the loop filter to say if I'm
lock or not ?

thanks

It's the bandwidth of the PLL - you need to increase the gain. Forget
all that BS about using state-machines.A multiplier is fine.When you
say that the signal is not there do you mean there is zero input or a
different freq?
PLL's need a carrier (clock) based input or the output can drift off.

F.

.

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