Digital PLL acquisition problem
- From: patrick.melet@xxxxxxxxxxxxx
- Date: 15 Mar 2007 08:46:13 -0700
Hi all,
I made a digital PLL, with multiplier based phase detector, digital
loop filter C1 + C2/(1-z^-1) and a digital NCO with 16 bits
accumulator
I want to lock on a 22170 Hz sine signal in 10 ms lock time
My problem is when I don't have the 22170 Hz signal, my output filter
sweep very slowly (1 second) beetween min and max of my input NCO and
don't lock when my 22170 Hz signal is on
So I put a window at the ouput of my filter to only sweep in a 2600 Hz
window
And when this ouput is out of this window I reset the filter
accumulator to its maximum value, now the ouput of the filter sweep
this window very slowly ( about 2 seconds)
So with this when I put my 22170 Hz off and on my loop locks into it,
but I have a very long lock time ( 200 ms) and not 10 ms...
Is in acquisition mode I have to "manually" sweep my input NCO in the
2600 Hz window and look at the ouput of the loop filter to say if I'm
lock or not ?
thanks
.
- Follow-Ups:
- Re: Digital PLL acquisition problem
- From: Tim Wescott
- Re: Digital PLL acquisition problem
- From: minfitlike
- Re: Digital PLL acquisition problem
- From: sampson164
- Re: Digital PLL acquisition problem
- From: Vladimir Vassilevsky
- Re: Digital PLL acquisition problem
- Prev by Date: Re: Lost with direct-form filter equations (inverting)
- Next by Date: help needed
- Previous by thread: PCA (Principal Components Analysis) Is it really adequate
- Next by thread: Re: Digital PLL acquisition problem
- Index(es):
Relevant Pages
|