Re: Digital Atten&Ampl. ?

Roger Bourne wrote:

If you accepted a wider output bus than the input it's perfectly
reasonable to ask for 100dB of attenuation in the stop band -- but you
_do_ have to make sure that your output bus is wide enough for it to
make sense.


This is a topic of interest to me:
Increasing the output bus (w.r.t input bus) of an IIR filter is giving
me a severe headache. Not in the implementaion sense of it, but rather
in the "what does it exactly mean?" kind of sense.

If the IIR filter input and output bus were the same width (number of
bits), then there would be no dilemma. You get a 16 bit data stream,
you dsp-filter it, and then you get the new filtered 16 bit data
stream. Voila, no problem.

But if the IIR filter output bus is bigger than the input bus, lets say
32 bits(O) and 16 bits(I), then the following question arise in my
head:
1. How is it possible to improve the accuracy of a data stream ? (Just
from a black box point of view, filtered data should have the number of
bits as the input data. Otherwise it is apples and oranges)
2. Are we really INCREASING the precision or are we rather attempting
to PRESERVE an existing infinite precison of ????? [something that I
can not put my thumb on].
3. If we really COULD increase the output precision with respect to the
input precision, then if we were to cascade several stages we could
obtain an extremely high precison from only several bits. That seems
mad. However, I get the impression that it is feasible and quite
common.
4. From where is this increased precision coming from? If my input of
the IIR filter is stemming from an ADC, how can the IIR filter
attribute a higher res than the ADC is already providing?

Please advise,

(and a big thanks for the preceding answers to my earlier posts)
-Roger

Let's do a thought experiment, then, in the grand tradition of the old Greek philosophers.

Let's say that you have a signal that can only take on the values 0 and 1 -- so it can be represented by just one bit in the grand old tradition of bits.

Now let's say that this signal is tied somehow to an analog signal, and done so in such a way that the _average_ value of the digital, 1-bit signal is exactly equal to the average value of the analog signal*.

If we were to take 16384 samples of that digital signal and averaged them, we'd have a much better idea of the value of the original analog signal than just '1' or '0'. Depending on how the digital signal is tied to the analog signal you could expect that the result of this 2^14 point sample would be good to anywhere between 7 and 14 bits**.

So a 'sensible' output from the averaging operation would have between 7 and 14 bits -- _not_ 1.

We have, in fact, answered questions 1 through 3 above -- the accuracy has been improved because there was high-frequency noise on the data that we've filtered out, the precision has indeed been improved, and we did it starting with just one bit to get 14.

A subject that is somewhat tangential to your question, but one which you may find useful, is sigma-delta converters. In a S-D ADC you take the output of a (usually) 1-bit DAC, subtract it from your signal of interest, filter it with an integrating filter, and run it to a (usually) 1-bit ADC. The output of this process is just one bit wide -- but there are fairly inexpensive 24 bit S-D ADCs out there. That's as much as you can expect from any ADC, and it presents a severe challenge to any front-end electronics you may use in front of the ADC. I have written a simplified article on sigma-delta DACs, which you can get to from http://www.wescottdesign.com/articles/sigmadelta.html; it may help.

As for question 4, well, think of averaging as just another low-pass filtering process. You can substitute the IIR low-pass filter of your choice and still see significant averaging going on. \

You used exactly the right word when you asked about extending ADC _resolution_, by the way. Your average 16-bit, 100ksps ADC will have internal noise in its front end, with an RMS value that's going to be several LSBs. This means that any one reading of the ADC could be off by many counts and still be within spec. It also means that several successive readings of the ADC will each be different from the other, but they will center around some value that's specific to the input value of the ADC but may not be the _right_ value (hitting the right value would be accuracy). If you take such an ADC and average its output you can get way more than 16 bits of resolution, even if you're not really improving the accuracy. This can be useful in motion control systems where short-term repeatability is essential but absolute accuracy isn't quite that critical.

* I'd say equal to the value of the analog signal, but it might be changing.

** Actually it could be worse than 7 bits, but never better than 14.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

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.

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