Re: Clock Multiplication Question

effimofunk wrote:
All,
I have a question regarding the implementation of a digital clock
multiplier. I am wondering if anyone has any tips of implementing an
all-digital integer clock multiplier. I have a system with a low rate
TCXO and I would like to run the digital portion of the mixed signal
design with a higher frequency. Adding another oscillator is not an
option and I believe there are some straightforward (somewhat) ways to
implement a clock multiplier in Digital Land. If anyone has a good tip or
a resource that discusses this I would appreciate any comments. I am
trying to take a 16.384 MHz TCXO and multiply it 4x to 65.536 MHz. Thanks
guys!

A digital phase-locked loop (such as a Costas loop) controlling a
numerically controlled oscillator comes to mind, but you need a faster
clock yet to build the NCO. I'm afraid that an analog quadrupler is the
simplest way. A pair of cascaded push-push doublers is very stable, but
a one-transistor version is feasible.

Many processors use an internal clock multiplier. As far as I know, they are analog oscillators phase locked to the lower clock.

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
.

Relevant Pages

  • Re: ACPI issue with ASUS P5A motherboard on 5.2-RELEASE
    ... I had GENERIC kernel installed and ACPI activated. ... any non-broken clock with a known frequency, as is done for the TSC ... But using the TSC is better anyway, since it has a higher quality than the ... away and sets the TSC frequency to (multiplier * i2854_freq) provided the ...
    (freebsd-current)
  • Re: Clock Multiplication Question
    ... I have a question regarding the implementation of a digital clock ... all-digital integer clock multiplier. ... TCXO and I would like to run the digital portion of the mixed signal ... numerically controlled oscillator comes to mind, but you need a faster clock yet to build the NCO. ...
    (comp.dsp)
  • Re: Virtex4 DCM in DRP mode
    ... ranging from 35 to 66 MHz in 2MHz increments by changing Multiplier ... The output drives CMOS imaging chip MT9V403. ... When I change the clock settings the imaging chips fails to ...
    (comp.arch.fpga)
  • How do I select an upgrade processor chip?
    ... somehow to the memory clock, but not in an integer way. ... The motherboard is capable of a faster FSB than it's set for. ... If I assume that the multiplier is locked, ... may cause the memory speed to change resulting in LESS performance. ...
    (comp.sys.ibm.pc.hardware.chips)
  • Re: Signed multiplication revisited
    ... better timing results on my code than on a simple A*B operation. ... XST will instantiate multiplier blocks ... Minimum input arrival time before clock: ... Maximum output required time after clock: ...
    (comp.lang.vhdl)