Re: PLL convergence problem
- From: allanherriman@xxxxxxxxxxx
- Date: 16 Oct 2005 22:08:01 -0700
Eric Jacobsen wrote:
> On 16 Oct 2005 10:38:08 -0700, allanherriman@xxxxxxxxxxx wrote:
>
> >This reminds me of a "learning experience" I had with a tracking
> >receiver design about 13 years ago. We could control the L.O.
> >frequency in a downconverter to produce a constant I.F. output
> >frequency, even though the carrier could vary by about 1/2 MHz (due to
> >doppler, etc.).
> >A narrowband 455kHz I.F. filter with a group delay of some ms was in
> >the feedback loop. The system would sometimes lock several kHz (?)
> >away from where it was supposed to be.
> >
> >I eventually found a paper that described the problem. I don't
> >remember all the details, but "As long that the loop bandwidth is
> >larger then
> >the frequency offset, the loop should converge to the right frequency"
> >is definitely false in the general case.
> >
> >A combination of high gain and delay caused the problem. Perhaps this
> >is why the leaky integrator helped - it reduced the gain at low
> >frequencies.
>
> Depending on what signals you were locking it probably just found a
> convenient false-lock point. Another way to prevent this sort of
> thing is to try to design the loop to have only one stable operating
> point, and that point being the desired lock frequency.
It turns out that there can be a large number of "stable" lock points
given these conditions:
- multiplier type phase detector.
- some delay
- high enough gain
- high C/N
The false locks are quite weak. My problem only showed up in the lab
(with an unrealistic C/N). There was also a hard limiter in the loop,
which meant the gain was huge if the C/N was high.
In the real world the signal from the satellite was quite noisy, and
only the main lock was stable.
The paper I read analysed the pullin problem something like this:
With an frequency offset on the VCO, there will be a beat signal at the
output of the phase detector. This gets filtered (with significant
attenuation if the offset frequency is large) and phase shifted by the
loop filter. The filtered and phase shifted beat signal then modulates
the VCO. This creates sidebands on the output of the VCO. One of the
sidebands is at the reference frequency. This produces some D.C. at
the phase detector output, which is what causes the loop to pull in.
However, the sign of the D.C. is determined by the phase of the
sideband, which is influenced by the delay in the loop filter. If
there's enough delay, it will actually push the VCO away from the
desired lock point.
(My apologies for any errors - I haven't thought about this for more
than a decade. There were pages of maths as well, no of which I can
remember, except that I had to solve sin(x) = kx to work out where the
lock points were.)
Regards,
Allan
.
- References:
- PLL convergence problem
- From: yoni.baron@xxxxxxxxx
- Re: PLL convergence problem
- From: Jerry Avins
- Re: PLL convergence problem
- From: Jerry Avins
- Re: PLL convergence problem
- From: allanherriman
- Re: PLL convergence problem
- From: Eric Jacobsen
- PLL convergence problem
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