Re: PLL convergence problem

On 16 Oct 2005 10:38:08 -0700, allanherriman@xxxxxxxxxxx wrote:

>This reminds me of a "learning experience" I had with a tracking
>receiver design about 13 years ago. We could control the L.O.
>frequency in a downconverter to produce a constant I.F. output
>frequency, even though the carrier could vary by about 1/2 MHz (due to
>doppler, etc.).
>A narrowband 455kHz I.F. filter with a group delay of some ms was in
>the feedback loop. The system would sometimes lock several kHz (?)
>away from where it was supposed to be.
>
>I eventually found a paper that described the problem. I don't
>remember all the details, but "As long that the loop bandwidth is
>larger then
>the frequency offset, the loop should converge to the right frequency"
>is definitely false in the general case.
>
>A combination of high gain and delay caused the problem. Perhaps this
>is why the leaky integrator helped - it reduced the gain at low
>frequencies.

Depending on what signals you were locking it probably just found a
convenient false-lock point. Another way to prevent this sort of
thing is to try to design the loop to have only one stable operating
point, and that point being the desired lock frequency. Sometimes
even just a dip in the overal tracking response can create essentially
the same condition as an equalizer that has found a local minimum in
the convergence space. It'll sit there and not move unless something
perturbs it to find a better lock point.

The leaky integrator is sometimes enough to make these local minima or
false lock points just unstable enough to make it move on to the next
(hopefully correct) stable operating point.

Anyway, that's just another way to look at it.


Eric Jacobsen
Minister of Algorithms, Intel Corp.
My opinions may not be Intel's opinions.
http://www.ericjacobsen.org
.

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