Re: DAC requirement for carrier generation


"Snowball" <sdris@xxxxxxxxxxxxxxx> wrote in message
news:dhef1f$r2t$1@xxxxxxxxxxxxxxxxxx
> Hi all,
>
> I would like to design a digital modulator using, say, M-QAM. For speed
> and
> simplicity, I am planning on using an FPGA development board that includes
> 160MSPS DACs. To avoid using extra hardware and interfacing to other
> boards,
> I would like to generate a digital carrier in the FPGA, then convert it to
> analog using the on-board DACs.
>
> My question is a general one: How many samples per carrier cycle are
> required in order to get a good analog (sinusoidal) signal at the output
> of
> my DAC? Since I can only process the digital data at 160MSPS with my DAC,
> I
> would be limited to a carrier frequency of 160/n MHz, where n=camples per
> carrier cycle (and hence I would like to know how to choose n!).
>
> Thanks in advance.
>
>
>
Sampling Frequency needs to be greater then the 2 * the highest frequency
you are generating.

so for 160MSPS, the a sinusoidal would need to be < 80MHz.

if you have a modulated carrier there with a bandwidth of say 2 MHZ, then
your fc would need to be < 79MHz so that the highest frequency is < 80MHz.
(fc + bw/2) < fs/2

fc = center frequency
bw = bandwidth
fs = sampling frequency

cheers,

Paul Solomon


.

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