100BASE-TX Scrambler Problem
- From: Woody Brison <woody.brison@xxxxxxxxx>
- Date: Thu, 12 Jun 2008 18:04:43 -0700 (PDT)
For 100BASE-TX, the scrambler is defined with 18 lines of Verilog
code. One could use some different circuit as long as it acts
exactly the same as this. That code I include below. If you will
refer to the part about 2/3 down in that defines the operation of
the flipflops in the LFSR... oh, WTH let's quote it right here:
always @(posedge txclk)
if (!txen)
ds[10:0] = #1 11'h0; // reset key stream
else if ( ds == 11'h0 )
ds[10:0] = #1 11'h1; // initialize key stream
else
ds[10:0] = #1 s[10:0]; // save current key stream
You will notice that when TXEN is deasserted, ie. between frames,
the LFSR is forced to all zeros (11 bits of value 0 expressed in
hex notation). When TXEN is reasserted, ie. a new frame starts,
the LFSR will be forced to state 00000000001 by that all zeros
detector on the line beginning "else if". After that it will step
thru all of its 2047 normal states in sequence, repeating ad
infinitum - until the end of frame when it will be forced to all
zeros again by TXEN going away.
This means that between frames, the scrambler outputs a stream of
all zeros. That means that the IDLE states issued by the 4b5b
encoder between frames will go out on the twisted pair. That means
that the cable will broadcast on a sharp tight 31.25 MHz, which
means that the FCC will be all upset. But this thing was designed
not to do that.
Where's the detail I'm missing here? How can this scrambler issue
anything but all zeros between frames?
Wood
_______________________________________________________
Verilog code
IEEE 802.3 Clause 25 refers us to ANSI X3.263-1995. The ANSI
standard was simply annexed to serve as Clause 25, with a very
few adaptations in terminology. The ANSI standard gives us this
Verilog code in Annex G:
G.2 Stream Cipher Scrambler Example
//
// STREAM CIPHER SCRAMBLER
//
// for bit serial data path with parallel key stream load
//
// txclk: transmit bit clock
// txen: transmit enable (disables scrambler)
// tnrzdin: unscrambled input NRZ data stream (plaintext)
// tnrzdout:scrambled output NRZ data stream (ciphertext)
//
module scrambler (txclk, txen, tnrzdin, tnrzdout);
input txclk, txen, tnrzdin;
output tnrzdout;
wire [11:0]s; // descrambler key stream
reg [10:0]ds; // key stream register
reg tnrzdout; // ciphertext output bit
//
// KEY STREAM
//
assign s[11:1] = ds[10:0]; // shift previous bits
assign s[0] = s[11] ^ s[9]; // generate newest bit
always @(posedge txclk)
if (!txen)
ds[10:0] = #1 11'h0; // reset key stream
else if ( ds == 11'h0 )
ds[10:0] = #1 11'h1; // initialize key stream
else
ds[10:0] = #1 s[10:0]; // save current key stream
//
// CIPHERTEXT STREAM
//
always @(posedge txclk)
tnrzdout = #1 s[0] ^ tnrzdin; // scramble NRZ data bit
endmodule
_______________________________________________________
.
- Follow-Ups:
- Re: 100BASE-TX Scrambler Problem
- From: Albert Manfredi
- Re: 100BASE-TX Scrambler Problem
- Prev by Date: Re: Mapping class D to Ethernet physical address
- Next by Date: Re: Want direct dialup access to my LAN
- Previous by thread: Mapping class D to Ethernet physical address
- Next by thread: Re: 100BASE-TX Scrambler Problem
- Index(es):
Relevant Pages
|
