Re: Question about 802.3 clause 24 - Transimit/Transmit-Bits state diagram

In article <1189559895.912309.124620@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
SuperJoe <ming_je@xxxxxxxxx> wrote:

Hi,

I have a very specific question about 802.3 clause 24 state diagram.
In Figure 24-7, Transmit Bits state diagram, looks like the state
transition happens every 8ns without interruption.

In Figure 24-8, Transmit state diagram, after "START STREAM K" state,
we need to start assigning ENCODE(TXD) data to tx_bits[4:0] in
"TRANSMIT DATA" state.
However, there is a extra latency for "ERROR CHECK" in between that
interrupts the "parallel-to-serial" function.

Could anyone explain to me because maybe I misunderstand the state
diagram?
Thanks a lot.


There is no "latency" (i.e., time delay) introduced by the ERROR CHECK
state. Section 24.4.7 (State Diagram Conventions) notes that the state
diagrams in Clause 24 follow the conventions of 21.5. Section 21.5.1
states that "actions inside a state block execute instantaneously." That
is, the state diagrams describe *functional behaviors*; they are not
flow charts for an implementation. By "instantaneously", we mean that
the actions occur much faster than external events, such that they incur
no significant latency.


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Rich Seifert Networks and Communications Consulting
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