Re: Pitfalls in interference graph ?

Rayiner Hashem a icrit :

Huh? Where is the dependence on sequential processing in graph
coloring allocation? Moreover, only a few non mainstream archs expose
non sequential semantics at the ISA level anyway.


Colouring hurts ILP extraction for both superscalar VLIW and EPIC
processors. Even if the ILP is not exposed at the architectural level,
compilers schedule operations to help the processor to extract it at
execution time.

If register allocation with coloring methods are used, the ILP of the
generated code would not be easily extracted by the processor at
execution time. Dynamic renaming is limited in practice (since the
window od instructions is limited).

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