comp.cad.synthesis

• Date Index

• [synopsys] struggling, stefimke
  • Re: struggling, Aditya Ramachandran
    • Re: struggling, Aditya Ramachandran
      • Re: struggling, stefimke
• autochar ?, mk
• Unsupported verilog construct with synopsys DC?, Fazela
  • Re: Unsupported verilog construct with synopsys DC?, michaelst@xxxxxxxxx
• Too big load in netlist after DC synthesis, gongguowang@xxxxxxxxx
  • Re: Too big load in netlist after DC synthesis, michaelst@xxxxxxxxx
  • Re: Too big load in netlist after DC synthesis, Aditya Ramachandran
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