comp.cad.synthesis
- Problem of generics with SDF simulation of VHDL design with Scirocco,
Fazela
- read_saif -scale problem,
SS
- synchr.and asynchr.,
Maryam
- Define clock in Synplicity,
Moises
- synopsys parallel case,
Maryam
- Pros/Cons of skew & latency?,
gopal
- Nanosim with Synthesized Verilog,
Sibi
- design compiler help,
mahalingamv@xxxxxxxxx
- TILOS circuit sizing,
mahalingamv@xxxxxxxxx
- problem with post synthesis simulation with Scirocco using sdf file,
Fazela
- seq and comb modules of the FPGA, pls HELP me out !!,
praviendre
- Inferring RAM with FOR loop,
vedpsingh
