Re: Definition of nets and subnets
- From: vlsidesign <fordgwf@xxxxxxxxx>
- Date: Fri, 16 May 2008 23:02:11 -0700 (PDT)
On May 16, 5:49 pm, vlsidesign <ford...@xxxxxxxxx> wrote:
Maybe this is the wrong forum for the question, but I am trying to
understand Cadence connectivity model better, and I think some of my
confusion is because I should better understand netlisting.
When do you mainly get subnets? Is it when you have a bus? If so, what
is the net called and what are the subnets?
For example,
Is there one net called 'bus[3:0]' that has four subnets called
bus[0], bus[1], bus[2] and bus[3]?
I think I found the information that has answered my question. The
bus[3:0] would seem to be four "terminals", which would then be four
separate nets. I included some information and there reference, in
case it may be useful for others.
-------------- vlehelp.pdf, page 222-223
Terminals expose a net up to the next level of the hierarchy. For
example, a master might have
10 nets and 4 terminals (associated with 4 of the nets).
When you create an instance of a master, it may have objects called
instTerms associated
with it. These instTerms map terminals in the instance’s master to
nets of the cellview in which
the instance has been placed. Virtuoso XL (or the Pick and Place
command) creates and
assigns these instTerms automatically. To expose these nets to the
next level of the hierarchy,
you create terminals for the nets, which are then mapped using
instTerms at the next level.
For example, consider the instance in the following figure, which
contains five pins: two on net
A, two on net B, and one on net C. These nets need to be available at
the next level of the
hierarchy, so you create three terminals named A, B, and C. 1
-------------- VXLConnAn.pdf, page 6-7
The term terminal corresponds to a logical connection in the symbolic
view of a device. The
term pin refers to a physical shape assigned to that terminal in the
layout.
As stated above, a single terminal on a device can have a number of
physical
pins.
.
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