Re: transistor parameters
- From: Riad KACED <riad.kaced@xxxxxxxxx>
- Date: Thu, 20 Mar 2008 07:21:32 -0700 (PDT)
Hi Medo,
1. This is related to your UMC pdk rather than the Cadence framework
itself.
The best way to find this information is to read the Design Rule
Manual or any documentation related to your process. The DRM usually
gives enough information about the layers and stuff ...
But if you want to use Cadence to get infos about :
You can either open (read-Only) the layout view of your MOS and "q"
the layers to find the one you're looking for. If you know the exact
name of the layer, just look for it in the LSW, either graphicall or
by skill :
(leSetEntryLayer list("layerName" "purpose")). This is case
sensitive ... This suppose your layer is already in the LSW.
Otherwise, use LSW -> Edit -> Set Valid Layers -> All Valid or in
skill :
(leSetLayerValid list("layerName" "purpose")).
There are plenty of skill functions to highlight layers ... but I'm
not really sure about what you are looking for precisely? More details
will help ...
As I said before, the golden reference is your pdk/drm documentation.
2. wphase function gives you the wrapped phase, i.e a phase which is
bounded around +/- 180.
Enjoy yourself !
Riad.
.
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