comp.cad.cadence

Date Index

Problem with gated clocks in RTL compiler, wantcar
NCELAB complains about 'negative timing check', wantcar
Example of verilog-a serial bit source., Poojan Wagh
- Re: Example of verilog-a serial bit source., Andrew Beckett
  - Re: Example of verilog-a serial bit source., Svenn Are Bjerkem
become a reseller, EMPIRE2D
S-parameter model, Verictor
- Re: S-parameter model, Andrew Beckett
Re: Using parameters in PWL data file, Andrew Beckett
Re: Ultrasim Waveforms while simulating, Andrew Beckett
Re: BSIM3v3 model file with statistical model block for Monte Carlo Simulation, Andrew Beckett
- <Possible follow-ups>
- Re: BSIM3v3 model file with statistical model block for Monte Carlo Simulation, Svenn Are Bjerkem
  - Re: BSIM3v3 model file with statistical model block for Monte Ca, okguy
gds file, Ken
- Re: gds file, Stewart Smith
- Re: gds file, Svenn Are Bjerkem
Custom Spectre circuit/subcircuit headers, Jake
Help. Cadence Spectre Simulation, qjin . research1
- Re: Help. Cadence Spectre Simulation, jayl-news
  - Re: Help. Cadence Spectre Simulation, fredo
    - Re: Help. Cadence Spectre Simulation, Svenn Are Bjerkem
Link a Symbol view to a subcircuit, Verictor
- Re: Link a Symbol view to a subcircuit, jayl-news
critical data access issue, Sylvio Triebel
- Re: critical data access issue, Andrew Beckett
Question for noise source, sfyen2004
- Re: Question for noise source, oliver
  - Re: Question for noise source, Andrew Beckett
Re: Are there the functions 'leEdgeSetLayer' and 'leEdgeAddAll' in skill?, John Gianni
- Re: Are there the functions 'leEdgeSetLayer' and 'leEdgeAddAll' in skill?, Andrew Beckett
Will there be a kit flow paper in the upcoming CDNLive in September?, Brenda Peters
- Re: Will there be a kit flow paper in the upcoming CDNLive in September?, dnh
  - Re: Will there be a kit flow paper in the upcoming CDNLive in September?, dnh
    - Re: Will there be a kit flow paper in the upcoming CDNLive in September?, Jim Tolar
Hierarchy list, Seagull
- Re: Hierarchy list, Risky
- Re: Hierarchy list, Risky
Re: Component Description Format, okguy
- Re: Component Description Format, Jean-Marc Bourguet
  - Re: Component Description Format, okguy
    - Re: Component Description Format, Andrew Beckett
split a polygon into group of rectangles, tadi
- Re: split a polygon into group of rectangles, S. Badel
Re: How to run skill code in test mode?, jayl-news
*WARNING* regarding incompatible design database revision, Ronny Boy
- Re: *WARNING* regarding incompatible design database revision, Andrew Beckett
SKILL Q: Other looping constructs besides "foreach?", Edward
- Re: SKILL Q: Other looping constructs besides "foreach?", jayl-news
  - Re: SKILL Q: Other looping constructs besides "foreach?", Edward
    - Re: SKILL Q: Other looping constructs besides "foreach?", Andrew Beckett
- Re: SKILL Q: Other looping constructs besides "foreach?", cadence
  - Re: SKILL Q: Other looping constructs besides "foreach?", Andrew Beckett
    - Re: SKILL Q: Other looping constructs besides "foreach?", cadence
VXL/Schematic Editor Annoyance: Losing Select Box, Edward
- Re: VXL/Schematic Editor Annoyance: Losing Select Box, Andrew Beckett
question of ocean script, rosemaryzywd
- Re: question of ocean script, oliver
Problem with joinableNet Function in Assura, mimirsbrun
LSW width, camelot
- Re: LSW width, Andrew Beckett
how does sp work?, fredo
- Re: how does sp work?, Andrew Beckett
  - Re: how does sp work?, fredo
fsdb to psf, anandganesan@xxxxxxxxx
- Re: fsdb to psf, Andrew Beckett
Seems like Wavescan lose contact with ADE from time to time ..., Svenn Are Bjerkem
- Re: Seems like Wavescan lose contact with ADE from time to time ..., Andrew Beckett
Finder - skill development, Michel
- Re: Finder - skill development, John Gianni
Skill Java Interface, Patrick
Few questions about power analysis in encounter, Koustav
HOT NWELL problems with assura, mimirsbrun
- Re: HOT NWELL problems with assura, Kholdoun TORKI
Running headless, excessiveness
- Re: Running headless, excessiveness
Dracula LVS of S/D, madan . v . kumar
Cadence Simulations using file, unforgiven@xxxxxxxxx
- Re: Cadence Simulations using file, Andrew Beckett
Virtuoso XL : create link Pcell <-> schematic, okguy
- Re: Virtuoso XL : create link Pcell <-> schematic, Jean-Marc Bourguet
  - Re: Virtuoso XL : create link Pcell <-> schematic, okguy
    - Re: Virtuoso XL : create link Pcell <-> schematic, Jean-Marc Bourguet
importing data in spectre, saurabhr8here
- Re: importing data in spectre, Andrew Beckett
Re: Option to change prompt color, Andrew Beckett
Re: Auto Placer Document, Andrew Beckett
Re: Postscript fonts with Virtuoso Composer, Andrew Beckett
nport in Spectre, Verictor
- Re: nport in Spectre, Andrew Beckett
probing extracted parasitic resistance from layout, s_kouchleva
Design Kit AMI 0.35um , Netlisting Problems, arnold_erni
- Re: Design Kit AMI 0.35um , Netlisting Problems, Andrew Beckett
Where're manuals of Assura DRC/LVS rules writing?, Reotaro Hashemoto
- Re: Where're manuals of Assura DRC/LVS rules writing?, jayl-news
  - Re: Where're manuals of Assura DRC/LVS rules writing?, Reotaro Hashemoto
    - Re: Where're manuals of Assura DRC/LVS rules writing?, jayl-news
Re: standalone skill interpreter, Patrick
- Re: standalone skill interpreter, Andrew Beckett
RE: skill Compiler, Patrick
- Re: skill Compiler, Andrew Beckett
How to get shorts, maddy
Select Results in ADE, gunnar . munder
open acces, danniel
How to access(plot) cds_global.\vdd! from OCEAN ?, -
- Re: How to access(plot) cds_global.\vdd! from OCEAN ?, S. Badel
  - Re: How to access(plot) cds_global.\vdd! from OCEAN ?, -
How can I get the instance property list ?, henger . chen
- Re: How can I get the instance property list ?, danniel
skill cadence, henger . chen
load data from file, danniel
- Re: load data from file, danniel
  - Re: load data from file, Andrew Beckett
Re: Is there any way to convert one layout view to skill code?, CM
- <Possible follow-ups>
- Re: Is there any way to convert one layout view to skill code?, Tim
  - Message not available
    - Re: Is there any way to convert one layout view to skill code?, S. Badel
x y coordinates, sajin
- Re: x y coordinates, S. Badel
  - Re: x y coordinates, noopster
opus on KDE 3.55, SS
- Re: opus on KDE 3.55, Pete nospam Zakel
- Re: opus on KDE 3.55, Stewart Smith
  - Re: opus on KDE 3.55, S. Badel
    - Re: opus on KDE 3.55, Nicolas
    - Re: opus on KDE 3.55, Svenn Are Bjerkem
    - Re: opus on KDE 3.55, cadence
    - Re: opus on KDE 3.55, Pete nospam Zakel
    - Re: opus on KDE 3.55, SS
Analog Artist Optimizer with SuSE, mgrossman
- Re: Analog Artist Optimizer with SuSE, Svenn Are Bjerkem
Bus, newborn
- Re: Bus, DReynolds
  - Re: Bus, newborn
    - Re: Bus, newborn
    - Re: Bus, S. Badel
    - Re: Bus, laya
gate sizing and interconnect delay, mahalingamv@xxxxxxxxx
locking a hierarchy with designsync, danmc
LVS in my cascode ...does it match or not?, Matteo
- Re: LVS in my cascode ...does it match or not?, Edward
  - Re: LVS in my cascode ...does it match or not?, Matteo
    - Re: LVS in my cascode ...does it match or not?, Matteo
VXL Q: Wire Editing Set-Up: "Can not get the master routing layer.", Edward
Corner analysis, Naren
- Re: Corner analysis, Svenn Are Bjerkem
Re: keypad (numbers on the right) map, Svenn Are Bjerkem
- Re: keypad (numbers on the right) map, rickm
  - Re: keypad (numbers on the right) map, Svenn Are Bjerkem
Re: VXL Q: How to break old, create new L/S association, Edward
Abstract Generator in Cadence, cyn . pettit
- Re: Abstract Generator in Cadence, Andrew Beckett
Inherited connections and explicit pins, Svenn Are Bjerkem
- Re: Inherited connections and explicit pins, danmc
- Re: Inherited connections and explicit pins, S. Badel
  - Re: Inherited connections and explicit pins, vtcad
    - Re: Inherited connections and explicit pins, Svenn Are Bjerkem
    - Re: Inherited connections and explicit pins, Andrew Beckett
  - Re: Inherited connections and explicit pins, Svenn Are Bjerkem
Results update using Analog Environment, Marko_Krcmar
- Re: Results update using Analog Environment, Svenn Are Bjerkem
  - Re: Results update using Analog Environment, Marko_Krcmar
    - Re: Results update using Analog Environment, Svenn Are Bjerkem
    - Re: Results update using Analog Environment, Marko_Krcmar
Input power in pss simulation, tkleeburg
- <Possible follow-ups>
- Input power in pss simulation, tkleeburg
- Input power in pss simulation, tkleeburg
pss simulation input power, tkleeburg
Speeding up the ocnPrint() function, Stephen Greenwood
- <Possible follow-ups>
- Speeding up the ocnPrint() function, Stephen Greenwood
  - Re: Speeding up the ocnPrint() function, Svenn Are Bjerkem
    - Re: Speeding up the ocnPrint() function, Stephen Greenwood
    - Re: Speeding up the ocnPrint() function, Andrew Beckett