comp.cad.cadence

• Date Index

• how to output simulation waveform, at
  • Re: how to output simulation waveform, Svenn Are Bjerkem
• CCAR inport to VXL fail, rickm
  • Re: CCAR inport to VXL fail, vlsidesign
    • Re: CCAR inport to VXL fail, rickm
• is there a procedure in SKILL to determine the bit of invoking icde/icfb?, bohu.seattle@xxxxxxxxx
  • Re: is there a procedure in SKILL to determine the bit of invoking icde/icfb?, Pete nospam Zakel
• Question about buses, nicholas . clark
• Preventing "crawling windows" in Cadence (running via XWIN), Jan Mikkelsen
  • Re: Preventing "crawling windows" in Cadence (running via XWIN), Pete nospam Zakel
  • Re: Preventing "crawling windows" in Cadence (running via XWIN), Svenn Are Bjerkem
• Debugging Analog Errors while simulating VHDLAMS behavioral code using Cadence Spectre, badam . bs
  • <Possible follow-ups>
  • Debugging Analog Errors while simulating VHDLAMS behavioral code using Cadence Spectre, badam . bs
• How to vary a schematic variable as a Gaussian distribution in Spectre?, Setu
• Use Spice model in Cadence, david . freedman
• netlist error, ponderboy
• fflush(stdout) for SKILL, vlasinvlad
  • Re: fflush(stdout) for SKILL, Suresh Jeevanandam
• creating a Verilog ams model, deepu
• check to see if a view is checked out, vlsidesign
  • Re: check to see if a view is checked out, vlsidesign
    • Re: check to see if a view is checked out, vlsidesign
• encounter problems, wzhenning
  • Re: encounter problems, S.Badel
    • Re: encounter problems, wzhenning
      • Re: encounter problems, wzhenning
• Finding power and operating point in Spectre WITHOUT ADE, sheikhmo@xxxxxxxxx
  • Re: Finding power and operating point in Spectre WITHOUT ADE, Andrew Beckett
• Failed to compile ahdlcmi module library, batik99
  • Re: Failed to compile ahdlcmi module library, Poojan Wagh
  • Re: Failed to compile ahdlcmi module library, Andrew Beckett
  • Re: Failed to compile ahdlcmi module library, DReynolds
• Create schematic from RCX extrated view, Tim
  • Re: Create schematic from RCX extrated view, S. Badel
    • Re: Create schematic from RCX extrated view, Tim
      • Re: Create schematic from RCX extrated view, Tim
      • Re: Create schematic from RCX extrated view, S.Badel
• Spectre question needs answer on cdnusers.org, LindaM
• Creating lists using OCEAN, sarathcvk@xxxxxxxxx
  • Re: Creating lists using OCEAN, Suresh Jeevanandam
    • Re: Creating lists using OCEAN, sarathcvk@xxxxxxxxx
• Simulating SOI circuit using Spectre, LindaM
• External applications within Cadence, kovalcik
  • Re: External applications within Cadence, jayl-news
• How to set the default path for new libraries in the library manager?, Svenn Are Bjerkem
• multiple globals in LVS, reubenwilcock
  • Re: multiple globals in LVS, S. Badel
• PSS Convergence Issue, atul . ee
• Re: skill:change drc error marker to metal layer, gerry@xxxxxxxxxxxxx
• Re: Need help in linear scaling of standard cell layout from 130nm to 90mn, gerry@xxxxxxxxxxxxx
• Simulating SOI with Spectre, AZ
• cadence wiki, Suresh Jeevanandam
  • Re: cadence wiki, Suresh Jeevanandam
• Cadence synthesis tool from VHDL to netlist?, EEngineer
  • Re: Cadence synthesis tool from VHDL to netlist?, Andrew Beckett
    • Re: Cadence synthesis tool from VHDL to netlist?, EEngineer
      • Re: Cadence synthesis tool from VHDL to netlist?, Andrew Beckett
• IC-Station-like strokes definition in Virtuoso, Reotaro Hashemoto
  • Re: IC-Station-like strokes definition in Virtuoso, jayl-news
  • Re: IC-Station-like strokes definition in Virtuoso, Andrew Beckett
    • Re: IC-Station-like strokes definition in Virtuoso, Reotaro Hashemoto
• using a port in sub-procedure, vlsidesign
  • <Possible follow-ups>
  • using a port in sub-procedure, vlsidesign
    • Re: using a port in sub-procedure, S. Badel
    • Re: using a port in sub-procedure, Suresh Jeevanandam
      • Re: using a port in sub-procedure, vlsidesign
• Custom IC Tips on cdnusers.org, LindaM
• CAD Engineer Wanted!! - Someone with a brain please apply.., rh0dium
• Where's my .cdsinit ???, Reotaro Hashemoto
  • Re: Where's my .cdsinit ???, S. Badel
    • Re: Where's my .cdsinit ???, Reotaro Hashemoto
      • Re: Where's my .cdsinit ???, S. Badel
      • Re: Where's my .cdsinit ???, Svenn Are Bjerkem
      • Re: Where's my .cdsinit ???, Bernd Fischer
      • Re: Where's my .cdsinit ???, Reotaro Hashemoto
      • Re: Where's my .cdsinit ???, Svenn Are Bjerkem
      • Re: Where's my .cdsinit ???, Andrew Beckett
      • Re: Where's my .cdsinit ???, Svenn Are Bjerkem
      • Re: Where's my .cdsinit ???, vlsidesign
• About SKILL ~> and -> Operators, Reotaro Hashemoto
  • Re: About SKILL ~> and -> Operators, sc
    • Re: About SKILL ~> and -> Operators, Reotaro Hashemoto
      • Re: About SKILL ~> and -> Operators, Suresh Jeevanandam
      • Re: About SKILL ~> and -> Operators, Suresh Jeevanandam
      • Re: About SKILL ~> and -> Operators, Andrew Beckett
  • Re: About SKILL ~> and -> Operators, S. Badel
• get CIW options from skill code, sc
• SKILL database object question, vlasinvlad
  • Re: SKILL database object question, Suresh Jeevanandam
• attn: lin - very delicious spam free nntp access - rec oz - (1/1), hilliard
• Extracting wire parasitic from silicon ensemble or other tool, nimayshah
  • Re: Extracting wire parasitic from silicon ensemble or other tool, gerry@xxxxxxxxxxxxx
• attn: leonora - enticing movies - ibge - (1/1), rik
• 64 bit linux and 64 bit icfb executable, SS
  • Re: 64 bit linux and 64 bit icfb executable, Andrew Beckett
    • Re: 64 bit linux and 64 bit icfb executable, SS
  • <Possible follow-ups>
  • 64 bit linux and 64 bit icfb executable, SS
• Width calculation, llipschutz@xxxxxxxxx
  • Re: Width calculation, AxisIC
  • Re: Width calculation, gerry@xxxxxxxxxxxxx
• running simulation is very slow, danniel
  • Re: running simulation is very slow, Svenn Are Bjerkem
    • Re: running simulation is very slow, danniel
      • Re: running simulation is very slow, Svenn Are Bjerkem
• gvim: doc string editing, jm.suresh@xxxxxxxxx
• Unkown icfb startup problem!! :(, Reotaro Hashemoto
  • Re: Unkown icfb startup problem!! :(, Reotaro Hashemoto
• Encounter Questions, wantcar
  • Re: Encounter Questions, AxisIC
    • Re: Encounter Questions, wantcar
      • Re: Encounter Questions, S. Badel
      • Re: Encounter Questions, wantcar
• Displaying parameter of internal component to the top-level block, MS_ASIC_LOVER
  • Re: Displaying parameter of internal component to the top-level block, Svenn Are Bjerkem
• Re: Slow Sun Ultra 45 graphics driving me mad!!, jelliott25
  • Re: Slow Sun Ultra 45 graphics driving me mad!!, Svenn Are Bjerkem
• "Rapid IP3" and other specialized analyses, Golana Rengised
• layout view, jutek
  • Re: layout view, AxisIC
• Re: adding connectivity to metal, rickm
• Cadence back-end! urgent help please!! :(, MS_ASIC_LOVER
  • Re: Cadence back-end! urgent help please!! :(, vlsidesign
    • Re: Cadence back-end! urgent help please!! :(, AxisIC
• Cadence Virtuoso ADE - Simulation and Plotting Help!, MS_ASIC_LOVER
  • Re: Cadence Virtuoso ADE - Simulation and Plotting Help!, Svenn Are Bjerkem
    • Re: Cadence Virtuoso ADE - Simulation and Plotting Help!, S. Badel
• gate-level simulation problem, Verictor
• assura limitataions, long run times?, rickm
• Generic differential design routing with CCAR, Farhaan
  • Re: Generic differential design routing with CCAR, vlsidesign
    • Re: Generic differential design routing with CCAR, Farhaan
      • Re: Generic differential design routing with CCAR, rickm
• required SKILL code to automate simulations, ahmad . abdulghany
  • Re: required SKILL code to automate simulations, Poojan Wagh
    • Re: required SKILL code to automate simulations, MS_ASIC_LOVER
      • Re: required SKILL code to automate simulations, Andrew Beckett
  • Re: required SKILL code to automate simulations, Svenn Are Bjerkem
    • Re: required SKILL code to automate simulations, Reotaro Hashemoto
• Re: Make LMHOSTID to output MAC in "UNIX format" when ran in linux, spectrallypure
  • <Possible follow-ups>
  • Re: Make LMHOSTID to output MAC in "UNIX format" when ran in linux, jayl-news
• Re: instPin is nil, vlsidesign
  • Re: instPin is nil, Suresh Jeevanandam
    • Re: instPin is nil, vlsidesign
      • Re: instPin is nil, Suresh Jeevanandam
      • Re: instPin is nil, vlsidesign
      • Re: instPin is nil, Suresh Jeevanandam
• Re: copying schematic of many cells in one cell, vlsidesign
  • Re: copying schematic of many cells in one cell, vlsidesign
• Re: How to use a DEF in SoC Encounter, vlsidesign
  • <Possible follow-ups>
  • Re: How to use a DEF in SoC Encounter, S. Badel
    • Re: How to use a DEF in SoC Encounter, Verictor
      • Re: How to use a DEF in SoC Encounter, S. Badel
      • Re: How to use a DEF in SoC Encounter, Verictor
      • Re: How to use a DEF in SoC Encounter, mk
      • Re: How to use a DEF in SoC Encounter, Verictor
• re-attaching library to different tech lib, vlsidesign
  • Re: re-attaching library to different tech lib, S. Badel
    • Re: re-attaching library to different tech lib, vlsidesign
• Removing the W,L,nf,m from Transistor in Schematics, amnon
  • Re: Removing the W,L,nf,m from Transistor in Schematics, Andy
• calibre DRC/LVS flow, maddy
  • Re: calibre DRC/LVS flow, vlsidesign
    • Re: calibre DRC/LVS flow, S. Badel
      • Re: calibre DRC/LVS flow, maddy
• Re: Is there anyway to compare two GDS files layer by layer?, Bernd Fischer
  • <Possible follow-ups>
  • Re: Is there anyway to compare two GDS files layer by layer?, Andy
  • Re: Is there anyway to compare two GDS files layer by layer?, gerry@xxxxxxxxxxxxx

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